Random number generator

This project shows a simple way to generate random numbers. Random numbers are used in many applications such as online games, 2 factor authentication, one time passwords cryptography, etc. There are various ways to generate random numbers. Usually, the numbers generated using digital algorithms are pseudo-random in nature as they are deterministic and repeat after certain states.

In this project I use the very popular Linear Feedback Shift register technique to generate random numbers. LFSR employs shift registers and XOR gates to generate random numbers.

The picture below shows the RTL Schematic of the LFSR implemented using VHDL in Vivado Design Suite.

--Code for LFSR Random Number Generator

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity pseudorng is
Port ( clock : in STD_LOGIC;
reset : in STD_LOGIC;
en : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (7 downto 0);
check: out STD_LOGIC);
end pseudorng;
architecture Behavioral of pseudorng is
signal Qt: STD_LOGIC_VECTOR(7 downto 0) := x"01";
begin
PROCESS(clock)
variable tmp : STD_LOGIC := '0';
BEGIN
IF rising_edge(clock) THEN
IF (reset='1') THEN
Qt <= x"01"; --for 0 it will enter redundant state of all 0's
ELSIF en = '1' THEN
tmp := Qt(4) XOR Qt(3) XOR Qt(2) XOR Qt(0);
Qt <= tmp& Qt(7 downto 1);
END IF;
END IF;
END PROCESS;
-- check <= temp;
check <= Qt(7);
Q <= Qt;
end Behavioral;

Testbench code -

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity tb_pseudorng is
end tb_pseudorng;

architecture bench of tb_pseudorng is

COMPONENT pseudorng
      Port ( clock : in STD_LOGIC;
      reset : in STD_LOGIC;
      en : in STD_LOGIC;
      Q : out STD_LOGIC_VECTOR (7 downto 0);
      check: out STD_LOGIC);
END COMPONENT;

signal clock1: STD_LOGIC;
signal reset1: STD_LOGIC;
signal Q1: STD_LOGIC_VECTOR(7 downto 0);
signal check1: STD_LOGIC;
signal en : STD_LOGIC;

begin

mapping: pseudorng PORT MAP(
clock => clock1,
reset => reset1,
en => en,
Q => Q1,
check => check1);

clock: PROCESS
BEGIN
   clock1 <= '0'; wait for 50 ns;
   clock1 <= '1'; wait for 50 ns;
END PROCESS;

reset: PROCESS
BEGIN
   reset1 <= '0';
   en <= '1';
   wait for 900 ns;
END PROCESS;

end bench;

On running the above code in Vivado, we can see that 8-bit random numbers are generated at each clock pulse. This LFSR can be modeled as a finite state machine with total number of states = 2^8 -1. As the all 0's state is of not use, we subtract 1.

This means a 8-bit LFSR will generate 255 distinct 8-bit random numbers which one can use for applications in simple games or even for simple cryptographic applications.

In the next part of this project, the generated random numbers will be transmitted wirelessly to another board using Amplitude Shift Keying Modulation technique.