PYNQ-Z2 HDMI Usage - 1: TPG Output

Introduction

I recently received a Pynq-Z2 development board. Since I’ve always been interested in image processing, this series will focus on image input, output, and processing. This post specifically demonstrates using the Pynq-Z2's HDMI output port to display TPG.

Before starting to create a project, we need to import the PYNQ-Z2 board file into Vivado 2022.2 so that we can select the PYNQ-Z2 as the target board.

• Vivado Version: 2022.2
• First, download the PYNQ-Z2 board file from this website.
• Next, extract the downloaded compressed file to the designated location within the Xilinx installation path.

Xilinx\Vivado\2022.2\data\boards\board_files

• Finally, open Vivado and, when you reach the board selection step, refresh the list to see the PYNQ-Z2 available.

Additionally, we also need the IP and XDC that will be used later in the design.

The IP must be downloaded from this website, and for the XDC, simply select "Master XDC" from this website.

OK, let's start by creating a project in Vivado 2022.2.

Create Project and Set IP

After creating the project, first click the "Settings" button in the top left corner, then navigate to the IP repository. On the right, click the plus (+) button and select the IP folder within the downloaded "vivado-library-master" directory. Once your selection is complete, click "Apply" and then "OK" to complete the import.

Next, click "Create Block Design." We will import several IP cores to integrate into our design. The IP cores used in this project include:

• ZYNQ7 Processing System

Integrates ARM Cortex-A9 processors with programmable logic, handling software execution, system control, and interfacing between hardware and software.

• Video Test Pattern Generator

Produces standard test patterns (e.g., color bars, grayscale) for verifying and calibrating the video pipeline without needing an external video source.

• Video Timing Controller

Generates and manages precise video timing signals (like horizontal and vertical sync), ensuring proper frame timing for smooth video display.

• AXI4-Stream to Video Out

Converts data from an AXI4-Stream interface into formatted video signals, bridging the gap between streaming data and video output.

• RGB to DVI Video Encoder

Encodes raw RGB video data into DVI-compliant signals, enabling connection to DVI displays by handling the necessary conversion and formatting.

• Clocking Wizard

It lets you configure multiple output clocks with specific frequencies, phases, and duty cycles to meet your design's timing requirements. By automating the selection and configuration of clock management hardware (like PLLs or MMCMs), the Clocking Wizard helps ensure that your design operates reliably while reducing manual effort.

Set the Output Clock to 148.5 MHz. Based on the resolution, 720P requires 74.25 MHz while 1080P requires 148.5 MHz. You can use this website for calculations.

After configuring all the IP cores, we can now proceed to connect them.

Connect IP

Click "Run Block Automation" to automatically configure the DDR and IO connections for the Zynq-7.

Connect the Zynq-7's FCLK_CLK0 to the Clock Wizard's input.

Then, link the relationships among the VTC, TPG, RGB2DVI, and AXI4-Stream to Video Out IPs.

Next, use Run Connection Automation to connect the clock (CLK) signals for all IP cores and the AXI Interconnect, ensuring that each CLK is set to 148MHz.

Then, manually complete the wiring connections that were not handled by the automation.

Since the TMDS output requires constraint definitions, you need to import the initially downloaded Master XDC file from Sources → Constraints.

Locate the HDMI TX-related definitions in the XDC file and uncomment them. Then, modify the corresponding pin assignments to match the naming conventions specified in the XDC file.

The hardware design is now complete.

Generate the XSA file

We will later use Vitis to write a driver that controls the TPG to generate a Color Bar effect. For this, we need to first generate an XSA file from Vivado.

First, convert the design_1_wrapper.bd file under the sources into an HDL representation. In Vivado, right-click the file and select "Generate HDL Wrapper". This step transforms your block design into a standard HDL file (Verilog or VHDL), which is necessary for synthesizing your design and integrating it with Vitis for driver development.

Next, you can simply click on "Generate Bitstream." Vivado will automatically initiate the synthesis, implementation, and other necessary processes, streamlining the entire bitstream generation workflow.

Finally, In Vivado, navigate to File → Export → Export Hardware. Be sure to check the option to include the bitstream if required, and then save the XSA file to your desired location.

The Vivado process is now complete.

Vitis Design Flow

Create Platform

Build Platform

Create Application on Platform

Open the helloworld.c file located in the Application/src folder and copy the following code into it.

#include <stdio.h>
#include "platform.h"
#include "xil_printf.h"
#include "xv_tpg.h"
XV_tpg tpg_inst;
int Status;
int main()
{
init_platform();
print("Hello World\n\r");
/* TPG Initialization */
Status = XV_tpg_Initialize(&tpg_inst, XPAR_V_TPG_0_DEVICE_ID);
if(Status!= XST_SUCCESS)
{
xil_printf("TPG configuration failed\r\n");
return(XST_FAILURE);
}
// Set Resolution to 1920x1080
XV_tpg_Set_height(&tpg_inst, 1080);
XV_tpg_Set_width(&tpg_inst, 1920);
// Set Color Space to RGB
XV_tpg_Set_colorFormat(&tpg_inst, 0x0);
//Set pattern to color bar
XV_tpg_Set_bckgndId(&tpg_inst, XTPG_BKGND_COLOR_BARS);
//Start the TPG
XV_tpg_EnableAutoRestart(&tpg_inst);
XV_tpg_Start(&tpg_inst);
xil_printf("TPG started!\r\n");
/* End of TPG code*/
cleanup_platform();
return 0;
}

Build the Application and program it onto the PYNQ-Z2 board. Once flashed, you'll see the result of the operation.

Result

Reference

Video Series 23: Generate a video output on Pynq-Z2 HDMI out