Norris Lin
Published © GPL3+

PYNQ-Z2 HDMI Usage - 2: HDMI Passthrough

On PYNQ-Z2, HDMI displays via TPG and supports rx/tx passthrough. See article 1 for TPG details; this article covers passthrough.

BeginnerFull instructions provided2 hours814
PYNQ-Z2 HDMI Usage - 2: HDMI Passthrough
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Things used in this project

Hardware components

PYNQ-Z2 board
AMD PYNQ-Z2 board
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Software apps and online services

Vivado Design Suite
AMD Vivado Design Suite
Vitis Unified Software Platform
AMD Vitis Unified Software Platform

Story

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Schematics

PYNQ-Z2 HDMI Passthrough Block Design

Code

hdmi_passthrough.c

C/C++
/******************************************************************************
*
* Copyright (C) 2009 - 2014 Xilinx, Inc.  All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* Use of the Software is limited solely to applications:
* (a) running on a Xilinx device, or
* (b) that interact with a Xilinx device through a bus or interconnect.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* XILINX  BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in
* this Software without prior written authorization from Xilinx.
*
******************************************************************************/

/*
 * helloworld.c: simple test application
 *
 * This application configures UART 16550 to baud rate 9600.
 * PS7 UART (Zynq) is not initialized by this application, since
 * bootrom/bsp configures it to baud rate 115200
 *
 * ------------------------------------------------
 * | UART TYPE   BAUD RATE                        |
 * ------------------------------------------------
 *   uartns550   9600
 *   uartlite    Configurable only in HW design
 *   ps7_uart    115200 (configured by bootrom/bsp)
 */

#include <stdio.h>
#include "platform.h"
#include "xil_printf.h"

#include "xv_tpg.h"
#include "xvidc.h"

XV_tpg Tpg;
XV_tpg_Config *Tpg_ConfigPtr;

#define TPG_Format	XTPG_BKGND_SOLID_WHITE

void XV_ConfigTpg() {


	u32 width, height;

	width = 1920;
	height = 1080;


	/* Stop TPG */
	XV_tpg_DisableAutoRestart(&Tpg);

	XV_tpg_Set_height(&Tpg, height);
	XV_tpg_Set_width(&Tpg, width);
	XV_tpg_Set_colorFormat(&Tpg, XVIDC_CSF_RGB);
	XV_tpg_Set_bckgndId(&Tpg, TPG_Format);
	XV_tpg_Set_ovrlayId(&Tpg, 0);


	/*
	 * Enable/Disable pass through mode based on whether sensor
	 * or TPG is selected
	 */

	XV_tpg_Set_enableInput(&Tpg, 1);


	XV_tpg_Set_passthruStartX(&Tpg, 0);
	XV_tpg_Set_passthruStartY(&Tpg, 0);
	XV_tpg_Set_passthruEndX(&Tpg, width);
	XV_tpg_Set_passthruEndY(&Tpg, height);

	/* Start TPG */
	XV_tpg_EnableAutoRestart(&Tpg);
	XV_tpg_Start(&Tpg);
}


void ResetVDMA()
{

	Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0x00, 0x00000004);
	Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0x30, 0x00000004);

}

void RunVDMAwithRegister(){

/////////////////////////// VDMA 0 /////////////////////////
	Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0x30, 0x8B);
	Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0xAC, XPAR_PS7_DDR_0_S_AXI_BASEADDR + 0x0000000);
	Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0xB0, XPAR_PS7_DDR_0_S_AXI_BASEADDR + 0x2000000);
	Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0xB4, XPAR_PS7_DDR_0_S_AXI_BASEADDR + 0x4000000);
	Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0xA8, 1920*3);
	Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0xA4, 1920*3);
	Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0xA0, 1080);


	Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0x00, 0x8B);
	Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0x5C, XPAR_PS7_DDR_0_S_AXI_BASEADDR + 0x0000000);
	Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0x60, XPAR_PS7_DDR_0_S_AXI_BASEADDR + 0x2000000);
	Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0x64, XPAR_PS7_DDR_0_S_AXI_BASEADDR + 0x4000000);
	Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0x58, 1920*3);
	Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0x54, 1920*3);
	Xil_Out32(XPAR_AXI_VDMA_0_BASEADDR + 0x50, 1080);
/////////////////////////////////////////////////////////////////////////////
}


int main()
{
    init_platform();
    int Status;

    ResetVDMA();
	RunVDMAwithRegister();

    /* Initialize TPG IP */
	Tpg_ConfigPtr = XV_tpg_LookupConfig(XPAR_V_TPG_0_DEVICE_ID);

	if (Tpg_ConfigPtr == NULL) {
		Tpg.IsReady = 0;
		return (XST_DEVICE_NOT_FOUND);
	}

	Status = XV_tpg_CfgInitialize(&Tpg, Tpg_ConfigPtr,
			Tpg_ConfigPtr->BaseAddress);
	if (Status != XST_SUCCESS) {
		xil_printf("ERR:: TPG Initialization failed %d\r\n", Status);
		return (XST_FAILURE);
	}

	XV_ConfigTpg();

    print("Successfully ran application");
    cleanup_platform();
    return 0;
}

Credits

Norris Lin
6 projects • 7 followers
An R&D professional passionate about FPGA development, skilled in system and IP integration.
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