4X4 Array Multiplier

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity fa is
    Port ( A : in STD_LOGIC;
           B : in STD_LOGIC;
           Cin : in STD_LOGIC;
           S : out STD_LOGIC;
           Cout : out STD_LOGIC);
end fa;

architecture Behavioral of fa is

begin
S <= ((A xor B) xor Cin);
Cout <= (((A and B) or (A and Cin) ) or (B and Cin));
end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity ha is
    Port ( A : in STD_LOGIC;
           B : in STD_LOGIC;
           S : out STD_LOGIC;
           C : out STD_LOGIC);
end ha;

architecture Behavioral of ha is

begin
S <= A xor B;
C <= A and B;

end Behavioral;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity arrm is
    Port ( X : in STD_LOGIC_VECTOR (3 downto 0) ;
           Y : in STD_LOGIC_VECTOR (3 downto 0) ;
           S : out STD_LOGIC_VECTOR (7 downto 0));
end arrm;

architecture Behavioral of arrm is
component andgate is
    Port ( A : in STD_LOGIC;
           B : in STD_LOGIC;
           C : out STD_LOGIC);
end component;

component ha is
    Port ( A : in STD_LOGIC;
           B : in STD_LOGIC;
           S : out STD_LOGIC;
           C : out STD_LOGIC);
end component;

component fa is
    Port ( A : in STD_LOGIC;
           B : in STD_LOGIC;
           Cin : in STD_LOGIC;
           S : out STD_LOGIC;
           Cout : out STD_LOGIC);
end component;
signal temp : STD_LOGIC_VECTOR(15 downto 0);
signal ic : STD_LOGIC_VECTOR(11 downto 0);
signal si : STD_LOGIC_VECTOR(11 downto 0);

begin
p0 : andgate port map(X(0),Y(0),S(0)); 
p1 : andgate port map(X(1),Y(0),temp(1)); 
p2 : andgate port map(X(2),Y(0),temp(2)); 
p3 : andgate port map(X(3),Y(0),temp(3)); 
p4 : andgate port map(X(0),Y(1),temp(4)); 
p5 : andgate port map(X(1),Y(1),temp(5)); 
p6 : andgate port map(X(2),Y(1),temp(6)); 
p7 : andgate port map(X(3),Y(1),temp(7)); 
p8 : andgate port map(X(0),Y(2),temp(8)); 
p9 : andgate port map(X(1),Y(2),temp(9)); 
p10 : andgate port map(X(2),Y(2),temp(10)); 
p11 : andgate port map(X(3),Y(2),temp(11)); 
p12 : andgate port map(X(0),Y(3),temp(12)); 
p13 : andgate port map(X(1),Y(3),temp(13)); 
p14 : andgate port map(X(2),Y(3),temp(14)); 
p15 : andgate port map(X(3),Y(3),temp(15)); 
l1 : ha port map (temp(1), temp(4) , S(1), ic(0));
l2 : fa port map (temp(5), temp(2),ic(0),si(0),ic(1));
l3 : fa port map (temp(6), temp(3), ic(1), si(1),ic(2));
l4 : ha port map (temp(7),ic(2), si(2), ic(3));
l5 : ha port map (temp (8), si(0), S(2),ic(4));
l6 : fa port map (temp(9), si(1), ic(4), si(3), ic(5));
l7 : fa port map (temp(10), si(2), ic(5), si(4), ic(6));
l8 : fa port map (temp(11), ic(3), ic(6), si(5), ic(7));
l9 : ha port map (temp(12), si(3), S(3), ic(8));
l10 : fa port map (temp(13),ic(8),si(4),S(4),ic(9));
l11 : fa port map (temp(14),ic(9),si(5),S(5),ic(10));
l12 : fa port map (temp(15),ic(10),ic(7),S(6),s(7));

end Behavioral;