Track and Hold Amplifier for an 8-bit ADC

The topology that has been used in this design is the Flip-around T/H circuit. The clocks ɸ1, ɸ1e and ɸ2 shown as phi1, phi1e and phi2 in the schematic are generated by Non-overlapping clock generator circuit. The clocks along with the AC input voltage are given through MOS switches to the negative input of the operational amplifier and the positive terminal is connected to VCM(AC ground).

The non-overlapping clock generator circuit contains a combination of NAND, NOT (Inverter) and Buffer Gates which produce the desired output. The schematics for the same are as follows:

The Operational Amplifier Circuit contains a basic 2-stage Op-Amp as follows:

The THA circuit inputs and constant sources from Op-Amp are as follows:

Vpulse(clkin) : v1 = 0V ; v2 = 5V ; tr(rise time) = tf(fall time) = 10ps ; pulse width = 100ns ; period = 200ns ; so, sampling frequency = 5MHz

Vdd: 5V

AC Input signal :3Vp-p(peak-to-peak) ; Signal frequency = 500kHz

AC Ground (VCM) : 2.5V

Constant current source (Id): 50µA

Hand Calculations & Estimation of Design Parameters

Cadence Simulation Results

The sampling frequency(fs) is 5MHz and the signal frequency(fsig) is 500kHz which basically means that fs is 10 times of fsig. In a period of 2µs, 10 samples of the output signal are taken. The clock ɸ1 is responsible for sampling the signal and clock ɸ2 is responsible for holding the signal after tracking it appropriately. Clock ɸ1e is for bottom plate sampling functionality.

Power Dissipation:

The power consumed by the Op-Amp is the static power and the power consumed due to operation of the switches and changes in current values at those nodes is called as dynamic power.

Static Power:

Method 1: Currents in all the branches of the 2 Stage op-amp are considered and DC voltage source of 5V (vdd) powers the circuit. Hence, Static Power = 13.92mW

Method 2: Differential inputs are removed and only common mode input VCM = 2.5V is applied. The test schematic for the same is shown below. The current at the power supply vdd is plotted against time and the average value of current is multiplied by the power supply voltage vdd=5V. Average value of current is calculated by the formula “ (integ(i(“/V7/PLUS” ?result “tran”) 0 2E-06)/2E-06) ’’ which gives I = 2.788mA. Hence, the static power is 2.79mA * 5V = 13.94mWwhich is equal to the value from Method 1.

Dynamic Power:

The test schematic for the dynamic power calculation includes the differential input signal and is as shown below. Average current is calculated from the formula “ integ(i("/V7/PLUS" ?result "tran") 0 2E-06 )/2E-06 ’’ which takes the average of current from the power supply node over the entire 10 clock cycles (2µsec), hence I = 2.782mA. Hence Total power = I*5V = 13.95mW.

Dynamic power = Total power – Static power = 13.95mW – 13.92mW = 0.03mW = 30uW

Static power / Total power = 13.92mW/13.95mW = 0.9978 , this implies that static power is 99.78% contributionof the total power implying that the op-amp consumes most of the power.

Dynamic power / Total power = 30uW/13.95mW = 0.00215, this implies that dynamic power is 0.215% contribution of the total power implying that the switch-capacitor SHA circuit consumes near to negligible amount of power.

Non-Overlapping Clocks:

The clocks are made to be non-overlapping and at the falling edge of clkin, ɸ1e falls to 0V earlier (switches OFF) than ɸ1, but both rise to 5V (switches ON) at the same time during the rising edge of clock input. ɸ2 rises (switches ON) and falls (switches OFF) complimentarily to ɸ1 and ɸ1e without overlap. This is as shown below:

Settling Error Simulation and Calculation:

As sampling frequency fs is 5MHz which is 10 times the signal frequency fsig of 500kHz, there are 10 samples of the input signal taken in one period. This can be observed in the zoomed in waveform below. The settling error at each of these samples is calculated to estimate the worst-case value as follows.

The formula “ sample(v("/net05" ?result "tran") 1.018315e-07 2e-06 "linear" 2e-07 ) ’’ has been used to sample the input signal starting at 101.8315ns (as this is the time value where ɸ1(sampling clock) is at 2.5V(50% of clock signal)) after every 200ns (clock period) until 2µs (input signal period).

The formula “ sample(lshift(v("/vout" ?result "tran") 1e-07 ) 1.024839e-07 2e-06 "linear" 2e-07 ) ’’ has been used to left shift the output signal by 100ns (as this is the pulse width of the clock) and then the shifted output is sampled starting at 102.4839ns(as this is the time value where ɸ2(holding clock) is at 2.5V(50% of clock signal)) after every 200ns(clock period) until 2µs(input signal period).

These formulae from the ADE L calculator generate the table as follows:

The settling error is calculated by subtracting the shifted input signal Vin(t-Dt) from Vout(t) and dividing that by the input amplitude 1.5Vp (as the sampling/holding is only on either half of Vp-p at any sample). The percentage of settling error is found by multiplying the obtained result by 100.

The obtained result of settling error (from calculator formulae) was tallied with samples taken manually and the results match as shown below for the highest settling error sample:

It can be observed in Fig.13 the output signal vout isn’t shifted to the left by 100ns(end of holding period) and hence the sample of output is taken when ɸ2 is 50%(2.5V) which is equal to 3.7292V. The input signal is directly sampled at 50% of ɸ1 at the point of tracking which is equal to 3.70848V. These values are in conjunction with the obtained results from ADE L calculator upon using the formulae. Hence, the settling errors calculated are validated through manual sampling.

Challenges

• Design of the non-overlapping clocks was tricky and the NAND, NOT, Buffer combination to achieve the same required constant design and testing.
• Rise and fall times have been included in the clock input to make the clocks ɸ1, ɸ2 and ɸ1e non-ideal

Learnings from Flip Around Circuit:

• First design of Flip circuit was able to track the circuit well but was not able to hold and had many ripples and peaking in the output due to low phase margin. Increasing the dc current and changing the compensation capacitor made it better.
• In the process on increasing Slew Rate, we had to compromise on phase margin. This resulted in ringing.
• It was also realized at the end of the design that ICMR could be increased to eliminate the ripples for larger input values. For lower inputs, the output obtained was ideal.

Conclusion

We have successfully designed and implemented Flip-Around Track and Hold Amplifier circuit which can be used in an Analog-to-Digital Converter(ADC).