Artix7 - 16bit CPU Design

module datapath
#(
   parameter BW = 16
)
(
  input                 clk,
  input                 start,
  input      [2:0]      sa,
  input      [2:0]      sb,
  input      [2:0]      dr,
  input      [4:0]      fs,  
  input			 [7:0]	  	pc,  
  input                 rw,         
  ///////mb,mm,md
  input                 mb,
  input                 md,
  input                 mm,
  
  input      [BW-1:0]   data_in,
  output     reg        vflg,
  output     reg        cflg,
  output     reg        nflg,
  output     reg        zflg,
  output     [BW-1:0]   data_out,
  output     [8:0]      addr_out,
  output     [BW-1:0]     r0_reg           
);

wire [BW-1:0] w_a, w_b, w_muxb, w_fun, w_muxd;
wire r_v_flag;
wire r_c_flag;
wire r_n_flag;
wire r_z_flag;

assign data_out = w_muxb;

always@(posedge clk or negedge start)
  if(!start) begin
    vflg<=0;
    cflg<=0;
    nflg<=0;
    zflg<=0;
  end else if(rw)begin
    vflg<=r_v_flag;
    cflg<=r_c_flag;
    nflg<=r_n_flag;
    zflg<=r_z_flag;
  end

//mux 2
mux_2t1 
#(
  .BW(BW)
)
mux_2t1_b
(
  .i_data_0(w_b),
  .i_data_1({13'b0,sb}),
  .sel(mb),
  .o_data(w_muxb)
);

mux_2t1 
#(
  .BW(9)
)
mux_2t1_m //9bit address
(
  .i_data_0(w_a[8:0]),
  .i_data_1({1'b0,pc}),//9bit
  .sel(mm),
  .o_data(addr_out)
);

mux_2t1 
#(
  .BW(BW)
)
mux_2t1_d //9bit address
(
  .i_data_0(w_fun), //16bit
  .i_data_1(data_in),//16bit
  .sel(md),
  .o_data(w_muxd)
);

register_file
register_file_u0
(
  .clk(clk),
  .reset_n(start),
  .i_data(w_muxd),
  .sa(sa),
  .sb(sb),
  .dr(dr),
  .en(rw),
  .o_a(w_a),
  .o_b(w_b),
  .reg_0(r0_reg)
);

function_unit
#(
  .BW(BW)
)
function_unit_u0
(
  .i_a(w_a),
  .i_b(w_muxb),
  .opcode(fs),
  .sa(sa),
  .v_flag(r_v_flag),
  .c_flag(r_c_flag),
  .n_flag(r_n_flag),
  .z_flag(r_z_flag),
  .o_fun(w_fun)
);
endmodule

`timescale 1ns/1ps

module br_unit
#(
  parameter   BW = 16
)
(
  input      [BW-1:0]   i_b,
  input      [2:0]      sel,//S2,S1,S0
  input      [3:0]      i_num, //fs[0],SA
  output reg [BW-1:0]   o_b
);
localparam  NO_SHIFT  = 3'b000;
localparam  LE_SHIFT  = 3'b001;
localparam  RI_SHIFT  = 3'b010;
localparam  AR_SHIFT  = 3'b011;
localparam  LE_ROTATE = 3'b100;
localparam  RI_ROTATE = 3'b101;
localparam  BR_ROTATE = 3'b110;
localparam  BL_ROTATE = 3'b111;

reg         [3:0]      r_num;
reg         [2*BW-2:0] r_b;
wire        [BW-1:0]   w_b_right;
wire        [BW-1:0]   w_b_left;

always@(*) begin
   case(sel)
      NO_SHIFT:  begin r_b = {i_b[14:0],i_b[15:0]};     r_num = 4'h0;  o_b = w_b_right; end
      LE_SHIFT:  begin r_b = {i_b[15:0],15'b0};         r_num = 4'h1;  o_b = w_b_left;  end
      RI_SHIFT:  begin r_b = {15'b0,i_b[15:0]};         r_num = 4'h1;  o_b = w_b_right; end
      AR_SHIFT:  begin r_b = {{15{i_b[15]}},i_b[15:0]}; r_num = 4'h1;  o_b = w_b_right; end
      LE_ROTATE: begin r_b = {i_b[15:0],i_b[15:1]};     r_num = 4'h1;  o_b = w_b_left;  end
      RI_ROTATE: begin r_b = {i_b[14:0],i_b[15:0]};     r_num = 4'h1;  o_b = w_b_right; end
      BR_ROTATE: begin r_b = {i_b[14:0],i_b[15:0]};     r_num = i_num; o_b = w_b_right; end
      BL_ROTATE: begin r_b = {i_b[15:0],i_b[15:1]};     r_num = i_num; o_b = w_b_left;  end
      default:   begin r_b = {i_b[14:0],i_b[15:0]};     r_num = 4'h0;  o_b = w_b_right; end
   endcase
end

genvar i;
generate
   for (i=0;i<BW;i=i+1) begin : br_gen_right
      mux_unit inst_mux_unit_right (r_b[i+BW-1:i], r_num, w_b_right[i]);
   end
endgenerate

generate
   for (i=30;i>BW-2;i=i-1) begin : br_gen_left
      mux_unit inst_mux_unit_left (r_b[i:i-(BW-1)], (BW-1)-r_num, w_b_left[i-(BW-1)]);
   end
endgenerate
endmodule