Programming the PL at Runtime with PetaLinux

Often at times we just want to use a new accelerator (static or partial) without needing to change the Linux kernel as we can compile application binaries on board. We can achieve PL programming via FPGA Manager on the Zynq devices when using PetaLinux / Linux.

This tutorial assumes a PetaLinux project is already created and in use on the board. If you would like know how to step Linux environment on FPGA board please refer to this tutorial.

Disclaimer: Make sure the AXI connections are not different from default boot up bitstream when doing runtime PL reconfiguration, specifically when using full bitstream. It may hang the system otherwise.

We execute the following steps in the bash shell, however, they can also be executed from C or python etc. using standard OS libraries.

Step 1: Preparing the bitstreams for runtime download:

• Convert.bit into.bin
• Source <Vivado_install_dir>/settings64.sh
• Create.bif file for your bitstream with the following content:

all:
{
  ./<Bitstream_name>.bit
}

• Use bootgen command to convert.bit into.bin:

bootgen -image <Input_file>.bif -arch zynqmp -o ./<Output_file>.bin -w

Step 2: Copy the.bin files to SD card

Step 3: Runtime reconfiguration

• Copy bitstreams into /lib/firmware
• Set the flags in FPGA Manager
• For full bitstream:

echo 0 > /sys/class/fpga_manager/fpga0/flags

• For partial bitstream:

echo 1 > /sys/class/fpga_manager/fpga0/flags

• Load Bitstream:

echo <Bitstream_name>.bin > /sys/class/fpga_manager/fpga0/firmware

See Xilinx documentation for further details: https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841847/Solution+ZynqMP+PL+Programming