FRAM interface with FM0+

Overview

The FM24V10 is a 1-Mbit nonvolatile memory employing an advanced ferroelectric process. The functional operation of the F-RAM is similar to serial (I2C) EEPROM. The major difference between the FM24V10 and a serial (I2C) EEPROM with the same pinout is the F-RAM's superior write performance, high endurance, and low power consumption. FM0+ controller is used as I2C master in the project.

Requirements

• Design Tool: IAR

• Programming Language: C for IAR

• Associated Devices: FM0+ S6E1B8, FRAM FM24V10

• Required Hardware: FM0-100L-S6E1B8 starter kit, CY8CKIT-042 BLE pioneer kit/FM24V10 IC

Hardware Setup

FM24V10 is present on CY8CKit042-BLE base board, the SDA and SCL lines are exposed as P5_0 and P5_1, pin 14 and pin 12 respectively on J10 of the base board.

Make the following connections between the two kits:

Refer to the schematics and user guides of both kits for more information for correct configuration of jumpers.

• http://www.cypress.com/documentation/development-kitsboards/fm0-100l-s6e1b8-arm-cortex-m0-mcu-starter-kit-usb-and-sd-card

• http://www.cypress.com/file/229211/download

Project details

FM0+ communicates with FM24V10 using I2C at 100kbps. MFS Channel 1 is used for I2C communication with 4.7Kohms external resistors as pull-ups for I2C lines. FM24V10 is present on Cy8CKit042-BLE base board, the SDA and SCL lines are exposed as P5_0 and P5_1, pin 14 and pin 12 respectively on J10 of the Baseboard. Setup snapshot is shown below:

The FRAM read and write data packet format is as shown below:

• The Write Buffer is 10 bytes consisting of the Write address as first two bytes and the next 8 bytes are data {1,2,3..8}.

• The 7 bit slave address of the FRAM is configured to be 0x50.

• FM0+ as I2C Master

• FM0+ is used as the I2C Master. I2C is configured using the MFS Block. In the master project, we specify the same slave address (0x50). Also, this slave address is converted to 8 bit slave address for Write and Read access by appending the Read or Write Bit at the LSB.

• MFS 1 is used to configure the I2C. Hence SOT1_2 and SCK1_2Pins are used. Necessary codes are provided for initializing the I2C Master, I2C Start and Stop conditions and I2C Read and Write access.

The Firmware Flow is as follows:

• I2C Master(FM0+) sends Start bit ,then sends Slave address with Write bit(0x50<<1& ~01 ).

• After receiving Ack ,it sends the write address location (0x0000) followed by 8 bytes of data.

• Once Write is successful, the write pointer of the slave is reset to offset address zero.

• Send the Slave address with read.

• After Ack from FRAM read 8 bytes of data and send Stop instruction

Testing:

The Master project attached here is based on PDL 2.1 template. The folder has three sub-folders names cmsis, drivers and S6E1BXF (device folder). IAR was used for testing the project.

• Ensure that you set the necessary directory paths under “Preprocessor” in the Project Build Settings. Please provide the paths to these folders. This depends on where you save the project.

• Ensure that mfs.c, pdl.c and pdl_user.h files are added to the Workspace:

For more details, you can refer to the PDL 2.1 Guide which can be downloaded from:

http://www.cypress.com/documentation/software-and-drivers/peripheral-driver-library-pdl

You can test the project by entering into the debug mode in IAR and placing breakpoint after Write and Read transactions and observe the values of TX and RX buffers in watch

You can also probe I2C lines SDA and SCL and analyze the data transmitted over I2C Bus.

Results:

Following are the scopeshot results for reading and writing from FRAM:

Write eight bytes of data from offset address 0x0000.

Figure 1 Write 8 bytes of data from address 0x0000

The read pointer is reset by writing the offset address to slave, In this case 0x0000.

I2C Master then sends start, followed by Slave address and read bit(50<<1|0x1),and it waits for Slave to write 8 bytes on the bus.

Figure 2 Read 8 bytes of data from offset address 0x0000