Secure Memory

Introduction

Keeping your data secure. This project aims to secure data from adversaries. It has inherent SRAM to keep the data safe and they are kept as not plaintext but ciphered. We got 5 macros inherently in order to accomplish our goal. The below section will be described those macros briefly.

Basic Macros

• TRNG - True random number generator. Ring oscillator macro which is one of the inner macros of the caravel core is used. In this macro, delay buffers are used instead of not gates. It can be also used as a key generator for AES.

• SPI - SPI pins are connected to GPIO pins which is spared for user project. User can read/write data from/to SRAM via SPI.
• UART - UART pins are connected to GPIO pins which is spared for user project. User can read/write data from/to SRAM via UART.
• AES - Cipher plaintext to keep data safe in SRAM.
• SRAM - Our precious. Its 1KB.

All these macros are in located in the verilog/rtl/ directory.

Links

• EFabless MPW-5 Project - https://platform.efabless.com/projects/800
• Github Repo - https://github.com/Procenne-Digital-Design/secure-memory

This project was created by Procenne-Digital-Design, and we are sharing it here to help spread the word about the EFabless Open MPW Shuttle Program.