Zynq Ultrascale+ Hello World in Vivado and Vitis

Introduction

Today we'll be walking through the entire process of creating a design for the ZCU104, from initial setup in Vivado to running a "Hello World" application in Vitis. The nice point about this "Hello World" is we run small logic in PL as well we run the application on PS and we show that both parts are alive.

Objective

In this video, we'll cover following objectives:

1. Creating a Vivado design with the ZYNQ Ultrascale+ IP, and blinking LED located in PL side.

2. Understanding board files presets, and comparing them with the schematic

3. Generating a bitstream, and exporting the hardware as XSA file.

4. Explaining the archived contents in XSA file.

3. Creating a Vitis project, and running a "Hello World" example

You can find full Video totarial here:

Block Diagram of design

This simple design demonstrates basic concepts of PS-PL interaction, clock distribution, and I/O control in a Zynq Ultrascale+ MPSoC system.

The Processing System block serves several important roles, although its full functionality isn't explicitly detailed in the diagram. here are the key functions of the PS block:

• Clock Generation: The primary visible role of the PS in this design is to generate and provide the clock signal for the Programmable Logic. This clock is crucial for driving the logic in the PL section.
• System Management: the PS typically handles overall system management.
• Potential Software Execution: The PS contains ARM processor cores capable of running complex software.
• Interface to External Systems: The PS often manages communication with external devices or systems through various interfaces (like, Ethernet, USB, UART), though this isn't shown in the current diagram.
• Configuration of PL: The PS is typically responsible for loading the bitstream that configures the PL with the desired logic design.

Let's break down how this system works step by step:

Processing System to Programmable Logic Clock:

• The PS provides a clock signal to the PL section. This clock is typically derived from the PS Phase-Locked Loop. The PS contains multiple PLLs for clock generation. The PS PLL can generate various frequencies; in this case, one of these PLLs is configured to generate the 100MHz clock.
• A 27-bit counter is implemented in the PL: The 27-bit counter driven by the 100MHz clock counts the clock pulses. It increments its value with each clock pulse.The counter’s output is a binary number that represents the count of clock pulses.
• Slice Block: Slice block is used to extract specific bits from the counter’s output.

In our design we will have a blinking LED, that after downloading the bitstream, it will start to blink, And it shows the generated clocks and everything is running properly in the PL side.

Vivado design

Create a new project with default board files for ZCU104

First, let's launch Vivado, once it's open, click on "Create Project" and choose a name and location for your project. Select "RTL Project" and check the box that says "Do not specify sources at this time."

Now, in the "Default Part" window, switch to the "Boards" tab. Here, we'll select the "ZCU104 Evaluation Board." This selection is crucial as it loads the correct board files for our project. These board files are located in your Vivado installation directory. They contain XML files that describe the board's components, interfaces, and preset configurations. Using these files ensures that we have the correct pin assignments and default settings for the ZCU104 board.

Adding ZYNQ Ultrascale+ IP

With our project set up, let's add the ZYNQ Ultrascale+ IP. In the Flow Navigator on the left, click on "Create Block Design." Once the diagram opens, click on "Add IP." and Search for "Zynq UltraScale+ MPSoC" and double-click to add it to your design.

You'll see a banner appear at the top of the diagram suggesting to run block automation. Click on "Run Block Automation, " select "Apply Board Preset", and click "OK." This process configures the IP with preset parameters that match the ZCU104 board layout.

Let's take a moment to appreciate what this automation has done for us. It's configured the Processing System interface to match the ZCU104 board layout. The DDR4 memory controller is set up for the on-board 4GB DDR4 memory. High-speed interfaces like USB 3.0, and DisplayPort are configured according to the board design. Low-speed interfaces such as UART, I2C, and SPI are mapped to the correct pins.

All these configurations align perfectly with the ZCU104 schematic, saving us a significant amount of time and reducing the chance of errors.

Exploring Peripherals and Schematic

Now, let's explore the peripherals in our design. If we expand the Zynq UltraScale+ IP block, we can see all the interfaces that have been configured.

Each of these interfaces corresponds directly to components and connections on the ZCU104 schematic.

When you choose block automation and apply board preset in Vivado, the selected MIO (Multiplexed I/O) pins indeed match the schematic shown in the images. This alignment between the software configuration and the hardware schematic is by design and provides several benefits:

1. QSPI (Quad SPI):

The preset selects MIO 0-5 for QSPI, which matches the schematic in Image 1. This covers the data lines (DQ0-DQ3), clock (CLK), and chip select (CS_B) pins.

2. SD Card:

The preset chooses MIO 46-51 for SD card interfacing, aligning with the schematic in Image. This includes data lines (DAT0-DAT3), command (CMD), and clock (CLK) pins.

3. Gigabit Ethernet MAC (GEM3):

The preset selects MIO 64-75 for GEM3, corresponding to the schematic in Image 2. This covers the various transmit and receive lines needed for Ethernet communication.

4. UART:

The preset configures MIO 18-19 for UART0 and MIO 20-21 for UART1, matching the schematic in Image. This sets up the transmit (TXD) and receive (RXD) lines for both UART interfaces.

5. I2C:

The preset selects MIO 16-17 for I2C1, which aligns with the information provided in Image.

6. CAN:

The preset chooses MIO 24-25 for CAN1, matching the schematic details in Image.

Understanding this concept is so important when you work with boards that are not provided with the board files! For such boards, you need to set each peripheral manually one by one. You will need to read the schematic and set the MIO pins based on the provided information.

Other parts in Vivado design

Let’s comeback to Vivado and continue our design now.

Add Counters and Slices:

Add a counter and change its bit width to 27 bits. Connect the clock of the counter to the PL clock zero.

Add a slice block to make the last bit of the counters as output. Make the slice’s output as external pin.

Deselect “High performance master ports”. Go to the PS-PL interface, master interface option and then deselect both HPM ports. For this design we don’t need the HPM ports, but in future when want to connect AXI blocks to processing system we will use them.

Validate and Wrap Up:

Validate the design and add the top wrapper. and let the Vivado to manage and auto handle it.

Generating Bitstream

Run Synthesis design and Wait until the Synthesis is finished

Open Synthesized design and Open I/O planning, Assign the proper pin for output to the LED and save it as a constrain file. You can find the GPIO LED from schematic or Board files.

Now you are ready to generate the bitstream!

Exporting the Hardware

The last step in Vivado is to export our hardware design for use in Vitis. Go to "File" > "Export" > "Export Hardware, " and make sure to check the "Include bitstream" option.

This process creates a.xsa (Xilinx Support Archive) file, which includes the hardware description, PS configuration, and PL bitstream. This file is the bridge between our hardware design in Vivado and our software development in Vitis.

For better understanding you can right click on the XSA file and extract it to a directory. You will find that it contains bitstream to program the PL side, and multiple PS initialization files. These initialization files follow the Processing system IP setup in Vivado.