Jogesh Singh
Bio
FPGA Design Engineer Likes Exploring Bits and Bytes
Joined
July 2021
Skills
RTL Design, FPGA Design, Hardware Description Languages
Location
Bangalore, Karnataka, India
Artix®-7 35T "Arty" FPGA Evaluation Kit
0 projects
Arty A7: Artix-7 FPGA Development Board
0 projects
Vivado Design Suite
1 project