Published June 6, 2023 © GPL3+

Xilinx FPGA-HDMI1.4: You Must Know First !

This in-depth article is what you should go first to be able to work with Industry-Standard FPGA HDMI designs. Don't Miss it!

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Xilinx FPGA-HDMI1.4: You Must Know First !

Things used in this project

Hardware components

Avnet ZedBoard

Software apps and online services

AMD Vivado Design Suite

AMD Vitis Unified Software Platform

Story

Overview

This design article gives you complete in-depth information that how the FPGA HDMI works. This will eventually cover FPGA board HDMI circuitry information, Vivado pipeline design, SDK application writing, and running the design on the board.

Keep reading!

You might be familiar with the different versions of HDMI. You might want to follow this Ref. to get more information. Out of several HDMI versions, this article will especially focus on HDMI1.4 Standard in order to interface with FPGA designs. For this purpose, I am considering some popular FPGA Evaluation/Development boards, for example, ZedBoard, ZC706, ZC702, VC707, KC705, AC701, and SP701. Because the HDMI output of these boards is HDMI1.4a Standard. Finally, I am going to use the standalone design approach. However, the same design can also be used in the Xilinx petalinux design approach with few design modifications. For a complete demonstration, I will take ZedBoard design as a reference. However, whichever FPGA boards use such a Transmitter IC, this article is still valid except for a few things.

After completing this article, you will be able to develop an HDMI video output interface on your own in order to display video/image processing output. I have skipped the detailed vivado pipeline design and SDK application development steps, as I am assuming that you guys have a general knowledge of it. Similarly, I am using Vivado/Vitis 2021.1.

HDMI1.4 in Xilinx FPGA Boards

Picture 1: HDMI1.4 Implementation in Xilinx FPGA Board

The Xilinx FPGA Development boards implement the HDMI1.4 standard using mostly Analog Devices HDMI ICs. These are ADV7611 and ADV7511. The first one is the HDMI Receiver IC while the second one is the HDMI Transmitter IC. If you notice, Xilinx FPGA boards mostly have HDMI output interfaces and ADV7511 HDMI ICs are already there. You must not get confused with HDMI2.0 and HDMI1.3 which some FPGA boards have. For lower-end FPGA boards, some board vendors include the HDMI1.3 interface. On the other hand, higher-end FPGA boards, such as Zynq UltraScale+ MPSoC boards, can support high-speed HDMI interface. So, they have HDMI2.0 interfaces. I will discuss both interfaces in future articles.

Let's come back to our topics.

If you are thinking why Xilinx FPGA boards are using Analog Devices ICs while there are other vendors. Well, this is because Analog Devices offers Linux drivers so that Xilinx's customers can leverage the Xilinx Petalinux tool to develop Linux applications on their own for HDMI-based designs.

ADV7511 HDMI Transmitter IC

Picture 2: ADV7511 HDMI Transmitter Pin Description

Picture 3: ADV7511 HDMI Transmitter IC Top View

Here are the key features of the ADV7511 HDMI IC.

Low power and high-speed HDMI Transmitter with Audio return channel (ARC)
It is compatible with HDMI 1.4 and DVI 1.0 standard
Programmable through slave I2C communication protocol.
Supports input data rate up to 165MHz and output data rate upto 225MHz
Supports the video format upto Full HD, 1080p@60Hz with maximum 36 bits per pixel
Supports both S/PDIF and 8-channel I2S audio. The S/PDIF can carry compressed audio including Dolby® Digital, DTS®, and THX®.
Supports a wide range of input and output formats as listed below,

Few Input formats

36, 30, or 24 bit RGB 4:4:4 (separate syncs)
36, 30, or 24 bit YCbCr 4:4:4 (separate syncs)
24, 20, or 16 bit YCbCr 4:2:2 (embedded or separate syncs)
36, 30, or 24 bit RGB 4:4:4 (separate syncs)
36, 30, or 24 bit YCbCr 4:4:4 (separate syncs)
24, 20, or 16 bit YCbCr 4:2:2 (embedded or separate syncs)

Few Output formats

36, 30, or 24 bit RGB 4:4:4
24 bit YCbCr 4:2:2
And so on

To get more information, you can find the datasheet link in the reference section of this article.

The IC is basically performing parallel to serial data conversion. Meaning, the IC receives the parallel video data from the FPGA logic as input and encodes them, and outputs them as an HDMI signal as shown in the picture below.

Picture 4: FPGA Parallel Data Encoding into HDMI Signal by ADV7511 IC

The IC supports a wide variety of input formats. For example, the input data bit can be from as few as 8-bit to as many as 36-bit. It can have either separate syncs or embedded syncs in the style of the ITU BT.656, SMPTE 274M, and SMPTE 296M specifications. The "Separate Syncs" means the IC has distinct pins for sync signal input. So, the input data and sync signals are separated from each other. On the other hand, the "Embedded Syncs" means the IC still has pins for sync signals but they are not used or grounded. Therefore, the input data has sync information embedded with the parallel data.

This can be observed in the following picture, highlighted by Blue Colors.

Picture 5: ADV7511 HDMI Transmitter IC with Separate Syncs(Left) and with Embedded Syncs (Right)

The following table summarizes various input formats supported by HDMI IC,

Picture 6: Various Input Format Description Table

Whichever FPGA boards or any other devices use ADV7511 HDMI IC, will have one of the above pin configurations.

Let's see how HDMI IC is configured in Zedboard, ZC702, ZC706, AC701, SP701, and VC707 boards.

Zedboard, KC705 & ZC702 HDMI Configuration

On these boards, the HDMI ICis configured with Input ID 1, that is, YCbCr 4:2:2 16-bit input with Separate Sync signals as you can notice in the above table.

The following picture is clearly showing the detailed pin configuration

Picture 7: YUV422 Format Pin Configuration

These boards' HDMI supports 3-styles of input data with right justification, as highlighted in the above picture. This information will also be needed while doing the register programming. Out of 36 bits, the bits from 8 to 23 are used for 16-bit parallel input data. The color component(Y, Cb and Cr) to be included in the parallel data is totally dependent on input data style and the no. of pixel. For example, in input style-1 with pixel 1, the bits from 8-15 are used for Y color component and bits from 16-23 are used for Cb color component as shown in the above picture.

To understand the above thing at the circuit level, let’s look at the HDMI schematics.

The following picture shows the ADV7511 HDMI Transmitter circuit schematic of ZedBoard/ZC702 and KC705 FPGA boards.

Picture 8: ZedBoard,KC705 and ZC702 ADV7511 Transmitter Circuit Schematic

Let's identify each signal as following

Picture 9: ZedBoard, ZC702 and KC705 HDMI Transmitter Signal Identification

Data Lines and Separate Syncs

Just like we noticed in the above input data mapping table, only the pins from 8 to 23 are used for 16-bit parallel YUV422 input data and there is also an HDMI clock. These are highlighted in Green Color. Meanwhile, other pins, highlighted in Gray Color, are not available to use. Similarly, as we learned that there are Separate Sync signals, these signals are highlighted by Blue Color in the above picture. There would not be such signals if the data pin was configured with Embedded Sync signals.

Programming Interface

ADV7511 IC is the programmable IC. Meaning, IC needs to be configured in order to work properly. This is done by doing the IC register programming by I2C Communication protocol. In the above image, the pins are highlighted in Yellow Color. The register programming details are discussed in the Code section of this article.

You can notice that the I2C pins are already pulled-up, we will not have to pull up these pins from the constraints.

HDMI Output Interface

The HDMI Output interface signals are highlighted in Red Color. These signals are generated after encoding the parallel data, sync signals and audio signals (if included). These signals go straight to the HDMI connector and are ready to be displayed on our HDMI monitor.

OtherInterfaces

This includes Audio Interface (SPDIF IN/OUT) and Interrupt(HDMI INT). In most, FPGA video designs, these signals are rarely used.

ZC706, AC701 and SP701 HDMI Configuration

HDMI Transmitter IC on these boards is configured with Input ID 0, that is, RGB/YCbCr 4:4:4 24-bit input with Separate Sync signals. To understand this, let's look at the following picture.

Picture 10: RGB/YUV444 Input Format Pin Description

Out of 36 bits, the bits from 4 to 11 are used for B/Cb color component, the bits from 16 to 23 are used for G/Y color component and the bits from 28 to 35 are used for R/Cr color component. Even though the Xilinx FPGA board's user guide is saying YCbCr format support, the pin configuration can also support RGB color format.

Let's look at the schematics.

Picture 11: ZC706, AC701, SP701 HDMI Transmitter Circuit Schematic

The following picture shows the ZC706/AC701/SP701 HDMI Transmitter Signal Identification.

Picture 12: ZC706, AC701, SP701 HDMI Transmitter Signal Identification

Just like we identified the signals in Zedboard, KC705, and ZC702 HDMI Transmitter schematic, we have similar signals in ZC706, AC701, and SP701 HDMI Transmitters.

Data Lines signals are highlighted in Green Color while Separate Sync signals are highlighted in Blue Color.
Programming Interface signals are highlighted in Yellow Color
HDMI Output Interface is highlighted by Red Color
Other interfaces are Audio Interface(HDMI_SPDIF IN/OUT) and HDMI Interrupt(HDMI_INT)

VC707 HDMI Configuration

HDMI Transmitter IC on VC707 boards is configured with Input ID 0, that is, RGB/YCbCr 4:4:4 36-bit input with Separate Sync signals.

Picture 13: RGB/YUV444 36-bits Input Format Pin Description

This is almost the same configuration as ZC706, AC701, and SP701 HDMI Transmitter but with 36-bit mode. However, VC707 HDMI Transmitter can support lower bit modes, for example, 30-bit and 24-bit modes, as shown in the above picture. These modes can be achieved by doing the bit manipulation in vivado block design.

The following picture shows the ADV7511 HDMI Transmitter circuit schematic of VC707 FPGA boards.

Picture 14: VC707 ADV7511 HDMI Transmitter

VC707 ADV7511 HDMI Transmitter has similar signals as we discussed in the previous sections. The following picture shows the signal identification.

Picture 15: VC707 HDMI Transmitter Signal Identification

Vivado Hardware Block Design

The signals that we have just identified in the above sections are really important to create the FPGA HDMI Output Display Pipeline correctly and efficiently. In this section, we will cover Vivado Pipeline Design by utilizing the above information.

The following picture shows the general view of interfacing between FPGA and ADV7511 HDMI Transmitter IC.

Picture 16: Interfacing between FPGA and ADV7511 HDMI Transmitter IC with Separate Syncs

On the FPGA side, the above picture represents the base-level pipeline that any ADV7511-based FPGA-HDMI design should have at least whether there is Zynq PS or Microblaze. However, this is only valid if FPGA ADV7511 HDMI Transmitter has been configured with separate sync signals.

Therefore, the following picture would be the least pipeline, if the Embedded Sync configuration is used. On the FPGA side, we will require Custom Logic/IP to get parallel data with embedded sync signals with it.

Picture 17: Interfacing between FPGA and ADV7511 HDMI Transmitter IC with Embedded Syncs

The following section gives you a brief description of each hardware block

Stream source

This represents the AXI4-Stream source, which can be the stream from HDMI input, Media devices, Memory buffers, or Test pattern generation IP block. In most cases, in the early stage of video pipeline design, the test pattern stream source is used, for example, Xilinx Video Test Pattern Generator (VTPG) IP is mostly used to replace the actual stream source and to verify/debug pipeline design. If the source has an RGB stream, it has to be converted into YUV422/YUV444 color format. If the source is directly able to give YUV422/YUV444, then obviously, the color conversion won't be necessary.

Video Timing

Picture 18: Video Timing Description

It includes the generation of video-related timing parameters, such as synchronization pulses, polarity, blanking period, active video signals, etc, as shown in the above picture. It is required to synchronize the processes and control the video data. Xilinx’s Video Timing Controller (VTC) IP can be used to generate timing signals for different video resolutions.

AXIS2Video

The AXI4-Stream conversion into Native video formats takes place here by the Xilinx AXI4-Stream to Video Out IP. This IP utilizes video timing information as well as streams to convert video data into displayable video format. This format includes parallel data and separate sync signals. The IP has one of the customization options to set desired output video color formats such as RGB, different YUV formats, etc.

Picture 19: Video Format Option

In most cases, the parallel data width is set according to the color format selected. For the current design case, the format is set in YUV422 (for ZedBoard, KC705, ZC702 HDMI Transmitter) will have 16-bit data and YUV444 (for ZC706, SP701, AC701, VC707 HDMI Transmitter) will have 24-bit data. In such a scenario, the source stream must have YUV422/YUV444 color format or if the source stream has RGB color format, then color conversion must be required to convert into YUV422 or YUV444 respectively before AXI4-Stream to Video Out IP.

Custom Logic/IP (Embedded Sync only)

If the ADV7511 HDMI Transmitter IC is done with Embedded Sync configuration, the AXIS2Video IP's output signals (parallel data + sync signals) will be required to convert and generate final parallel data output with embedded syncs.

IIC

Xilinx's AXI IIC IP plays a major role in implementing the I2C communication protocol in order to program the HDMI Transmitter IC.

Clock Generator

This is necessary for the design to get the required clock signals to drive the entire FPGA pipeline including the video clock. Xilinx’s Clocking Wizard IP is most popularly used in such a case. The IP can get clock input from an external clock oscillator or the Zynq PS block and then generate various user-defined clock outputs. The video clock is generated according to the output video resolution.

Zynq PS/Microblaze

This forms the processing system of the design, where the application will be loaded and run to control and configure the processing system itself, board peripherals, and the pipelines in the programmable logic(PL).

You can find all of the above IPs' product guide links in the reference section.

Finally, when we acknowledge the above pipeline design flow, we get the vivado pipeline designs as follows.

Here, the color conversion has been avoided, because VTPG will be configured to give YUV422/YUV444 stream.

The following design represents the base-level design for ZedBoard, ZC706, and ZC702

Picture 20: Zynq SoC Based Vivado Design for Zedboard, ZC706 and ZC702

The following design represents the base-level design for SP701, AC701, KC705, and VC707

Picture 21: Microblaze Based Vivado Design for SP701, AC701, KC705 and VC707

The pipeline is designed to generate the 1080p@60Hz video output, which will be fed to ADV7511 IC to get HDMI output to display on the HDMI monitor. The pipeline will only be able to work properly, when

The video clock is 148.5MHz (for 1080p@60Hz) and AXI4 Stream Clock is greater or at least equal to Video Clock
the VTC IP is configured with generation mode with 1080p video mode. Note that AXI4-Lite has not been enabled in the above design.
VTPG IP is configured to give output in YUV422 (for ZedBoard, KC705, ZC702) or YUV444 (for ZC706, AC701, SP701, VC707) color format
AXIS2 Video Out IP is configured with output color format YUV422 (for ZedBoard, KC705, ZC702) or YUV444 (for ZC706, AC701, SP701, VC707), as we discussed in the previous sections of this article.
ADV7511 IC is properly programmed by I2C.

Constraints

Picture 22: FPGA Constraint Mapping

Without constraints, the signal will never be able to come out from the FPGA chip and Vivado also does not allow the generation of design until the design is properly constrained. Whenever the designs have floated pins or ports, constraint mapping must be done.

While manufacturing the FPGA boards, some of the FPGA physical pins are already soldered to some specific board peripherals, for example, external clock, HDMI Input/Output, etc and the constraint helps the FPGA design signals to be physically connected to those FPGA physical pins safely. That’s why the FPGA development boards have the master constraints file, which can conveniently be used in the design to map the pins and ports quickly.

Zedboard, KC705, ZC702, ZC706, AC701, SP701, and VC707 FPGA board already have the master constraint files, you can find its link in the reference section of this article.

1 / 6 • SP701 ADV7511 HDMI Constraint

When you open the XDC file, you can find the details of the above pin, which includes, I2C, DE, HSync, Vsync, 16-bit data, interrupt(INT), and audio pins mapping. Note that, when you open Xilinx's Master XDC file, you will find ungrouped constraints. Therefore, except for Zedboard HDMI constraints, I have grouped and ordered all the HDMI constraints of the rest of the boards to make you feel easy.

The Blue highlighted pins are the actual FPGA physical pins, which are already soldered with the ADV7511 IC input signal pins (as highlighted in the schematics). The Red highlighted pins are the ports of our pipeline that we just created in Vivado. And finally, the Yellow Highlighted constraint line is really important that you must not forget. Because it sets the IOSTANDARD for our ports. However, most master constraint files already have this constraint line included. So, you might not need to worry.

Once this constraint is applied, the red highlighted pins will be connected to blue highlighted pins with specified IOSTANDARDs so that, the video data signals get their way to the HDMI IC safely.

IMPORTANT! Probably, you might have noticed that in the above constraint description, Zedboard andSP701 has a dedicated I2C constraint while ZC702,ZC706,AC701,KC705, andVC707 do not have I2C constraint information.

Let's look once yourself. Did you find the difference?

I believe yes.

This is because ZC702, ZC706, AC701, KC705, and VC707 have an onboard I2C Switch to communicate various peripherals including HDMI Transmitter IC. Xilinx has mostly used TI Semiconductor PCA9548 1-to-8 channel I2C bus switch. This information will also be required while programming.

The following pictures show the I2C switch used in the ZC702/706/AC701/KC705/VC707 boards

1 / 5 • ZC706 I2C Switch

The Red highlights show the HDMI I2C path from FPGA.

SDK Application

Once the design generation completes, we can move to SDK Application development using Vitis. As we proceed with this, the following two things have to be done.

Initialization and configuration TPG to generate YUV422 (for Zedboard/KC705/ZC702) or YUV444 (for ZC706/AC701/SP701/VC707) color bar pattern in 1080p resolution
AXI IIC IP Initialization and Configuration to program the ADV7511 HDMI TX IC. Here, we do the programming of various registers of HDMI IC according to IC programming guide. Check the reference section. Here, we also need to have the information of I2C path, I2C switch address (0x74) and the address of the IC itself (0x72). For the case of ZedBoard/SP701 board, we directly program the ADV7511 IC. For the case of ZC702/706/AC701/KC705/VC707, we have to setup a complete I2C path from FPGA to IC. For this, we have to program the I2C switch to open HDMI I2C channel and then program the ADV7511 IC. For example, if we considered ZC706, the I2C switch has to be programmed 0x02 (00000010). This is because, If we look at the I2C switch block diagram as shown in the above picture, Out of 8 I2C channels, the HDMI I2C lies at channel 1. You can also follow the same way for other boards, After this, we have to program the ADV7511 IC as discussed in the following section.

The following shows the quick information on register programming that should be done at least.

IMPORTANT! The first two registers (0x15 and 0x16) are programmed according to the ADV7511 Input Data configuration as shown in picture 6 above.

All the values are in HEX.

<IC address> <Register Address> <Value>

72 15 01; Input color format YUV422 with Separate Syncs (for Zedboard/KC705/ZC702)

Or,

72 15 00; Input color format RGB or YUV444 with Separate Syncs (for ZC706/AC701/SP701/VC707)

Similarly,

72 16 B8; 0x16[7]- Output color format 422, 0x16[5:4]-Input Color Depth 8 bits, 0x16[3:2]-Input Video Style 1 (for Zedboard/KC705/ZC702)

If you remember, just as we discussed in the previous section, Zedboard/KC705/ZC702 boards' HDMI supports 3-styles of input data. 0x16[3:2] value can be varied according to this information.

Or,

72 16 30; 0x16[7]- Output color format 444, 0x16[5:4]-Input Color Depth 8 bits, 0x16[3:2]- Style not valid (for ZC706/AC701/SP701)

Or,

72 16 20; 0x16[7]- Output color format 444, 0x16[5:4]-Input Color Depth 12 bits, 0x16[3:2]- Style not valid (for VC707)

0x16[5:4] value can be varied to support 8-bit/10-bit color depth.

Following register programming is done to set the coefficients for Color Conversion from YUV to RGB. The value is set according to the value given in tables 56 and 57 (from the ADV7511 programming guide) for HDTV. Currently, table 56 register values are used.

other register programs.

72 41 10; Power down
72 48 08; Right justification of video input (for only Zedboard/KC705/ZC702)
72 55 00; Set RGB in AVinfo Frame
72 56 28; Set Aspect Ratio 16:9, Active Format Aspect Ratio as Aspect Ratio
72 98 03; ADI Recommended Write
72 9A E0; ADI Recommended Write
72 9C 30; PLL Filter R1 Value
72 9D 61; Set Clock Divide
72 A2 A4; ADI Recommended Write
72 A3 A4; ADI Recommended Write
72 AF 04; HDMI Mode, HDCP Disable, Frame Encryption Disable
72 BA 60; No input video clock delay
72 E0 D0; Must be set to 0xD0 for proper operation
72 F9 00; This should be set to a non-conflicting I2C address (set to 0x00)

Finally, once we cover the above programming steps, it completes our SDK application development.

Remember! VTC does not need to be programmed becauseAXI4-Lite is not enabled.

We have to build and run the design on the board. This development flow is valid for all the above-mentioned boards. So, for the complete code reference and the output demonstration, I have used the ZedBoard. Check the Demonstration section for a complete step-by-step design video on ZedBoard. Check CodeSection for a complete code reference.

Output

When everything is set, we should get the color bars output as shown in the following picture.

Picture 23: ZedBoard ADV7511 HDMI Output

----------------------------------
 ZedBoard-ADV7511 HDMI Output Demo
----------------------------------

TPG Configuration
HDMI Configuration
Register Programming...DONE!

Register Programming Verification
Reg Addr: 0x15------Write Data: 0x1------Read Data: 0x1------Matched
Reg Addr: 0x16------Write Data: 0x38------Read Data: 0x38------Matched
Reg Addr: 0x41------Write Data: 0x10------Read Data: 0x10------Matched
Reg Addr: 0x48------Write Data: 0x8------Read Data: 0x8------Matched
Reg Addr: 0x55------Write Data: 0x0------Read Data: 0x0------Matched
Reg Addr: 0x56------Write Data: 0x28------Read Data: 0x28------Matched
Reg Addr: 0x98------Write Data: 0x3------Read Data: 0x3------Matched
Reg Addr: 0x9A------Write Data: 0xE0------Read Data: 0xE0------Matched
Reg Addr: 0x9C------Write Data: 0x30------Read Data: 0x30------Matched
Reg Addr: 0x9D------Write Data: 0x61------Read Data: 0x61------Matched
Reg Addr: 0xA2------Write Data: 0xA4------Read Data: 0xA4------Matched
Reg Addr: 0xA3------Write Data: 0xA4------Read Data: 0xA4------Matcheda
Reg Addr: 0xAF------Write Data: 0x6------Read Data: 0x6------Matched
Reg Addr: 0xBA------Write Data: 0x60------Read Data: 0x60------Matcheda
Reg Addr: 0xE0------Write Data: 0xD0------Read Data: 0xD0------Matched
Reg Addr: 0xF9------Write Data: 0x0------Read Data: 0x0------Matched
Reg Addr: 0x18------Write Data: 0xAC------Read Data: 0xAC------Matched
Reg Addr: 0x19------Write Data: 0x53------Read Data: 0x53------Matched
Reg Addr: 0x1A------Write Data: 0x8------Read Data: 0x8------Matched
Reg Addr: 0x1B------Write Data: 0x0------Read Data: 0x0------Matched
Reg Addr: 0x1C------Write Data: 0x0------Read Data: 0x0------Matched
Reg Addr: 0x1D------Write Data: 0x0------Read Data: 0x0------Matched
Reg Addr: 0x1E------Write Data: 0x19------Read Data: 0x19------Matched
Reg Addr: 0x1F------Write Data: 0xD6------Read Data: 0xD6------Matched
Reg Addr: 0x20------Write Data: 0x1C------Read Data: 0x1C------Matched
Reg Addr: 0x21------Write Data: 0x56------Read Data: 0x56------Matched
Reg Addr: 0x22------Write Data: 0x8------Read Data: 0x8------Matched
Reg Addr: 0x23------Write Data: 0x0------Read Data: 0x0------Matched
Reg Addr: 0x24------Write Data: 0x1E------Read Data: 0x1E------Matched
Reg Addr: 0x25------Write Data: 0x88------Read Data: 0x88------Matched
Reg Addr: 0x26------Write Data: 0x2------Read Data: 0x2------Matched
Reg Addr: 0x27------Write Data: 0x91------Read Data: 0x91------Matched
Reg Addr: 0x28------Write Data: 0x1F------Read Data: 0x1F------Matched
Reg Addr: 0x29------Write Data: 0xFF------Read Data: 0xFF------Matched
Reg Addr: 0x2A------Write Data: 0x8------Read Data: 0x8------Matched
Reg Addr: 0x2B------Write Data: 0x0------Read Data: 0x0------Matched
Reg Addr: 0x2C------Write Data: 0xE------Read Data: 0xE------Matched
Reg Addr: 0x2D------Write Data: 0x85------Read Data: 0x85------Matched
Reg Addr: 0x2E------Write Data: 0x18------Read Data: 0x18------Matched
Reg Addr: 0x2F------Write Data: 0xBE------Read Data: 0xBE------Matched
Register Programming Successful!

Demonstration

You can visit the following link to see a complete design demonstration.

References

What next?

This article presented you with the fundamental FPGA design to work with HDMI1.4 Standard by interfacing the ADV7511 HDMI TX IC. You can follow this design flow to work with other Xilinx/Vendor FPGA boards that include ADV7511 HDMI TX IC. It can be integrated with higher FPGA designs. In your custom design, you can replace the VTPG IP with the actual input source. This design uses a Standalone design approach for a better startup. In future designs, I will bring up the design with the Linux approach and will also discuss HDMI2.0, and HDMI2.1.

I hope you like this article.

Do not forget to like, share and follow!

Code

/* main.c
 *
 * 		Author: Nikil Thapa
 *
 */
#include "platform.h"
#include "xil_printf.h"
#include "xv_tpg.h"
#include "xvidc.h"
#include "hdmi_config.h"

XV_tpg tpg;

void ConfigTpg() {
	XV_tpg_Initialize(&tpg, 0);
	XV_tpg_DisableAutoRestart(&tpg);
	XV_tpg_Set_height(&tpg, 1080);
	XV_tpg_Set_width(&tpg, 1920);
	XV_tpg_Set_colorFormat(&tpg, XVIDC_CSF_YCRCB_422);
	XV_tpg_Set_bckgndId(&tpg, XTPG_BKGND_COLOR_BARS);
	XV_tpg_Set_ovrlayId(&tpg, 1);
	XV_tpg_Set_boxSize(&tpg, 100);
	XV_tpg_Set_motionSpeed(&tpg, 10);
	XV_tpg_EnableAutoRestart(&tpg);
	XV_tpg_Start(&tpg);
}

int main() {

	print("----------------------------------\n\r");
	print(" ZedBoard-ADV7511 HDMI Output Demo\n\r");
	print("----------------------------------\n\r");

	print("\n\r");
	print("TPG Configuration\n\r");
	ConfigTpg();

	print("HDMI Configuration\n\r");
	hdmi_config(XPAR_AXI_IIC_0_BASEADDR);

	return 0;
}

/*
 * hdmi_config.c
 *
 * Author: Nikil Thapa
 *
 */
#include "hdmi_config.h"

#define PAGE_SIZE	16
#define IIC_ADV7511_ADDRESS 0x39
#define NUMBER_OF_HDMI_REGS  40
#define EEPROM_TEST_START_ADDRESS	0x80

#define EEPROM_ADDRESS		0x50

typedef struct {
	u8 addr;
	u8 data;
	u8 init;
} HDMI_REG;

HDMI_REG hdmi_iic[NUMBER_OF_HDMI_REGS] = {

		{ 0x15, 0x00, 0x01 },
		{ 0x16, 0x00, 0x38 },
		{ 0x41, 0x00, 0x10 },
		{ 0x48, 0x00, 0x08 },
		{ 0x55, 0x00, 0x00 },
		{ 0x56, 0x00, 0x28 },
		{ 0x98, 0x00, 0x03 },
		{ 0x9A, 0x00, 0xE0 },
		{ 0x9C, 0x00, 0x30 },
		{ 0x9D, 0x00, 0x61 },
		{ 0xA2, 0x00, 0xA4 },
		{ 0xA3, 0x00, 0xA4 },
		{ 0xAF, 0x00, 0x06 },
		{ 0xBA, 0x00, 0x60 },
		{ 0xE0, 0x00, 0xD0 },
		{ 0xF9, 0x00, 0x00 },
		
		// HDTV YCbCr (16to235) to RGB (16to235)
		//color space conversion
		/**/{ 0x18, 0x00, 0xAC },
		/**/{ 0x19, 0x00, 0x53 },
		/**/{ 0x1A, 0x00, 0x08 },
		/**/{ 0x1B, 0x00, 0x00 },
		/**/{ 0x1C, 0x00, 0x00 },
		/**/{ 0x1D, 0x00, 0x00 },
		/**/{ 0x1E, 0x00, 0x19 },
		/**/{ 0x1F, 0x00, 0xD6 },
		/**/{ 0x20, 0x00, 0x1C },
		/**/{ 0x21, 0x00, 0x56 },
		/**/{ 0x22, 0x00, 0x08 },
		/**/{ 0x23, 0x00, 0x00 },
		/**/{ 0x24, 0x00, 0x1E },
		/**/{ 0x25, 0x00, 0x88 },
		/**/{ 0x26, 0x00, 0x02 },
		/**/{ 0x27, 0x00, 0x91 },
		/**/{ 0x28, 0x00, 0x1F },
		/**/{ 0x29, 0x00, 0xFF },
		/**/{ 0x2A, 0x00, 0x08 },
		/**/{ 0x2B, 0x00, 0x00 },
		/**/{ 0x2C, 0x00, 0x0E },
		/**/{ 0x2D, 0x00, 0x85 },
		/**/{ 0x2E, 0x00, 0x18 },
		/**/{ 0x2F, 0x00, 0xBE }

};

u8 IIC_DEVICE_ADDR; 

u8 WriteBuffer[PAGE_SIZE];

u8 ReadBuffer[PAGE_SIZE];

u8 DataBuf[PAGE_SIZE];

typedef u8 AddressType;

int hdmi_config(u32 IIC_BASEADDR) {
	u8 BytesRead;
	u32 StatusReg;
	u8 Index;
	int Status, i;
	int count = 0;
	IIC_DEVICE_ADDR = 0x74;
	u8 buffer;
	u8 Addr;
	u8 DataInit;

	Status = XIic_DynInit(IIC_BASEADDR);
	if (Status != XST_SUCCESS) {
		return XST_FAILURE;
	}
	while (((StatusReg = XIic_ReadReg(IIC_BASEADDR, XIIC_SR_REG_OFFSET))
			& (XIIC_SR_RX_FIFO_EMPTY_MASK | XIIC_SR_TX_FIFO_EMPTY_MASK
					| XIIC_SR_BUS_BUSY_MASK))
			!= (XIIC_SR_RX_FIFO_EMPTY_MASK | XIIC_SR_TX_FIFO_EMPTY_MASK)) {

	}

	for (Index = 0; Index < PAGE_SIZE; Index++) {
		WriteBuffer[Index] = Index;
		ReadBuffer[Index] = 0;
		DataBuf[Index] = 0;
	}
	print("Register Programming...");
	IIC_DEVICE_ADDR = IIC_ADV7511_ADDRESS;
	for (Index = 0; Index < NUMBER_OF_HDMI_REGS; Index++) {
		IIC_WRITE(IIC_BASEADDR, hdmi_iic[Index].addr, &hdmi_iic[Index].init, 1);

	}
	print("DONE!\n\r");

	print("\n\rRegister Programming Verification\n\r");
	for (Index = 0; Index < NUMBER_OF_HDMI_REGS; Index++) {

		Addr = hdmi_iic[Index].addr;
		DataInit = hdmi_iic[Index].init;
		xil_printf("Reg Addr: 0x%x------Write Data: 0x%x------", Addr,
				DataInit);
		BytesRead = IIC_READ(IIC_BASEADDR, Addr, &buffer, 1);
		for (i = 0; i < 1000; i++)
			;	// IIC delay
		xil_printf("Read Data: 0x%x------", buffer);

		if (DataInit == buffer) {
			xil_printf("Matched\n\r");
			count++;
		} else {
			xil_printf("Not-Matched\n\r");
		}

		if (BytesRead != 1) {
			return XST_FAILURE;
		}
	}
	if (count == NUMBER_OF_HDMI_REGS) {
		xil_printf("Register Programming Successful!\n\r");
	} else {
		xil_printf("Register Programming FAILED!\n\r");
	}

	return XST_SUCCESS;
}
u8 IIC_WRITE(u32 IIC_BASEADDR, AddressType Address, u8 *BufferPtr, u8 ByteCount) {
	u8 SentByteCount;
	u8 WriteBuffer[sizeof(Address) + PAGE_SIZE];
	u8 Index;

	if (sizeof(AddressType) == 2) {
		WriteBuffer[0] = (u8) (Address >> 8);
		WriteBuffer[1] = (u8) (Address);
	} else if (sizeof(AddressType) == 1) {
		WriteBuffer[0] = (u8) (Address);
		IIC_DEVICE_ADDR |= (EEPROM_TEST_START_ADDRESS >> 8) & 0x7;
	}


	for (Index = 0; Index < ByteCount; Index++) {
		WriteBuffer[sizeof(Address) + Index] = BufferPtr[Index];
	}


	SentByteCount = XIic_DynSend(IIC_BASEADDR, IIC_DEVICE_ADDR, WriteBuffer,
			sizeof(Address) + ByteCount,
			XIIC_STOP);

	return SentByteCount - sizeof(Address);
}
u8 IIC_READ(u32 IIC_BASEADDR, AddressType Address, u8 *BufferPtr, u8 ByteCount) {
	u8 ReceivedByteCount;
	u8 SentByteCount;
	u16 StatusReg;


	do {
		StatusReg = XIic_ReadReg(IIC_BASEADDR, XIIC_SR_REG_OFFSET);
		if (!(StatusReg & XIIC_SR_BUS_BUSY_MASK)) {
			SentByteCount = XIic_DynSend(IIC_BASEADDR, IIC_DEVICE_ADDR,
					(u8 *) &Address, sizeof(Address),
					XIIC_REPEATED_START);
		}

	} while (SentByteCount != sizeof(Address));

	ReceivedByteCount = XIic_DynRecv(IIC_BASEADDR, IIC_DEVICE_ADDR, BufferPtr,
			ByteCount);

	return ReceivedByteCount;
}

Credits

Nikil Thapa

6 projects • 25 followers

FPGA Computer Vision Design Expert.

Xilinx FPGA-HDMI1.4: You Must Know First !

Things used in this project

Hardware components

Software apps and online services

Story

Overview

HDMI1.4 in Xilinx FPGA Boards

Zedboard, KC705 & ZC702 HDMI Configuration

ZC706, AC701 and SP701 HDMI Configuration

VC707 HDMI Configuration

Vivado Hardware Block Design

Constraints

SDK Application

Output

Demonstration

References

What next?

Schematics

Microblaze_HDMI_BD

Zynq_HDMI_BD

Code

main.c

hdmi_config.c

hdmi_config.h

Credits

Nikil Thapa

Comments

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Xilinx FPGA-HDMI1.4: You Must Know First !

Xilinx FPGA-HDMI1.4: You Must Know First !

Things used in this project

Hardware components

Software apps and online services

Story

Overview

HDMI1.4 in Xilinx FPGA Boards

Zedboard, KC705 & ZC702 HDMI Configuration

ZC706, AC701 and SP701 HDMI Configuration

VC707 HDMI Configuration

Vivado Hardware Block Design

Constraints

SDK Application

Output

Demonstration

References

What next?

Schematics

Microblaze_HDMI_BD

Zynq_HDMI_BD

Code

main.c

hdmi_config.c

hdmi_config.h

Credits

Nikil Thapa

Comments

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