VC707 Board Interface Test Flow

This article primarily describes how to conduct official peripheral functionality tests on the VC707.

• Vivado Version: 2021.1
• The process is a port from Vivado 2014.1 to 2021.1.
• The attached vc707_bist/system.tcl file has been updated for Vivado version 2021.1. If you need to use another version, please modify it accordingly.

Build VC707 Board Interface Test(BIST) on Vivado

Open Vivado → Create and Package New IP, and extract the downloaded VC707 BIST file.

• You can directly download the attached vc707_bist.zip.

Select "Package a specified directory, " and then choose the vc707_bist/gtxe2_top_v1_00_a/hdl folder from the extracted files.

Package the IP and create the VC707 BIST Block Design.

Select the MIG IP in the Block Design and change Clock 0 to 200 MHz.

Add the constraint file to the Sources.

Create HDL Wrapper and Generate Bitstream

Export XSA

Build VC707 BIST Application on Vitis

Open Vitis and import the XSA file exported from Vivado to create a Platform.

Build Platform

Create an Application Project on the previously generated Platform.

Import the program files from vc707_bist\vc707_bist.sdk\bist_app\src.

Modify the variable names for ReadBuffer, WriteBuffer, and InterruptController in xilflash_protection_example.c.

Modify the value of MEM_OFFSET in bram_mem_test_example.c.

Build and execute the BIST program on VC707.

And It Works！