Saqib Awan

3 Projects4 Followers2 Following
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Bio

Hardware Engineer and Embedded Systems Enthusiast | Passionate about SoCs, RFSoCs, and Cutting-Edge Hardware Design

Joined

April 2021

Skills

FPGA, Digital Signal Processing , AMD Xilinx

Location

Islamabad, Islamabad Capital Territory, Pakistan

Projects
This tutorial shows how to generate FPGA IP cores using Vitis Model Composer, from modeling to deployment—step by step.
FPGA IP Core Generation with Vitis Model Composer
852
HIL Simulation: MATLAB to generate signal from Picoscope, digitize it using XADC(Zybo), receive it back from PS RAM, plot, and FFT in MATLAB
Hardware-in-the-Loop Simulation with MATLAB and Zyob-Z7
126
Using XADC on ZYBO Z7-20 to digitize function generator signals, transfer via DMA, and plotting in MATLAB.
Digitizing Signals with XADC on ZYBO Z7-20
525
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