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Saqib Awan

3 Projects 5 Followers 2 Following

This tutorial shows how to generate FPGA IP cores using Vitis Model Composer, from modeling to deployment—step by step.

FPGA IP Core Generation with Vitis Model Composer

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HIL Simulation: MATLAB to generate signal from Picoscope, digitize it using XADC(Zybo), receive it back from PS RAM, plot, and FFT in MATLAB

Hardware-in-the-Loop Simulation with MATLAB and Zyob-Z7

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Using XADC on ZYBO Z7-20 to digitize function generator signals, transfer via DMA, and plotting in MATLAB.

Digitizing Signals with XADC on ZYBO Z7-20

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