Steve Hoover

2 Projects 6 Followers 0 Following

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September 2018

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We are enabling a new model of computing by providing a framework for writing web applications that utilize custom hardware acceleration.

Hardware Accelerated Web Applications Using Cloud FPGAs

1.2K

WARP-V is an implementation of the RISC-V ISA that showcases the powerful modeling techniques provided by Transaction-Level Verilog.

WARP-V: The Most Flexible RISC-V CPU Core Generator

1.7K

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Cardboard VR SDKs

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