Basic Hardware Design for Arty A7 in Vivado 2022.1

The Arty-A7 is a handy little FPGA development board for AMD-Xilinx's 7series Artix chips. The Artix-7 is a 28nm device with a high performance-per-watt fabric for its low price point. The Artix is also one of my first choices for projects with a tight power budget so the Arty-A7 is a common development board for me to reach for. This project walks through the hardware design in Vivado for a good starting point for bare-metal application development utilizing the peripherals available to the Artix FPGA on the Arty-A7.

There are two versions of the Arty-A7 with different fabric size Artix-7s: the Arty A7-35T and Arty A7-100T. I'm using the A7-35T for this project, but the only difference in this write-up if you're using the A7-100T would be selecting it was the target board instead of the A7-35T when initially creating the Vivado project.

Note: I'm using Vivado 2022.1 in this write-up, but should work in any other 202x.x versions as far as I am aware.

Create Vivado Project

Launch Vivado and create a new project targeting the Arty A7 board. This is a regular RTL project, so be sure to leave the option to make the project an extensible Vitis platform unchecked. Also leave the option to not specify any source files in this point checked.

Some manufacturers create board preset files for their Xilinx-based FPGA development boards that contain configuration/pinouts for elements that a user can't change such as the FPGA's connections to peripherals on the PCB.

Since Arty is a Digilent FPGA development board, its board preset files are available in the Xilinx Board Store repository that Vivado has a backend connection to.

Use the refresh button to make sure Vivado is pointing to the latest version of the Xilinx Board Store repository. Search for the Arty version being targeted (the A7-35 or A7-100) and download the files if they haven't been downloaded previously.

Click Finish and wait for Vivado to launch into a fresh project targeting the Arty A7.

Create Block Design

The Artix-7 supports the use of AMD-Xilinx's soft processor, the MicroBlaze. The easiest way to instantiate and configure a MicroBlaze in Vivado is via the Block Design graphical GUI.

From the Flow Navigator window, select the option for Create Block Design. You can give it a custom name if desired, or leave it as the default.

The new blank block design will automatically open for you to start adding IP blocks to.

The first thing to add is the MicroBlaze soft processor IP block (this is an HDL implementation of a processor).

A green banner will appear at the top of the Block Design window with the option to run Block Automation. This applies the minimum configuration necessary to boot up the MircoBlaze.

While it's not necessary, I do recommend enabling the option to add the Interrupt Controller. This comes in handy later when developing the software to run on the MicroBlaze.

After running Block Automation the option to run Connection Automation will pop up.

This will automatically connect the system clock and reset ports to the MicroBlaze system.

The connection automation may connect the system clock as a differential, so you can fix that by deleting the differential clock port, then connecting it using the Board tab:

Connect clocking wizard and processor system reset input reset signal to the same external reset port:

When an FPGA development board is selected as the target for a Vivado project (versus just a specific FPGA part number), there is an extra tab available in the Block Design GUI called Board. This tab is where a user can select which of the peripherals on the target FPGA development board to connect to the RTL in the Block Design.

Right-click on each peripheral and select the option to Connect Board Component. A window will pop up with a list of compatible IPs for the peripheral to connect to.

Use the Board tab to connect the following peripherals (Selected IP from Connect Board Component window):

• System Clock (clk_wiz_1) - overriding connection automation from earlier
• Ethernet MII (AXI EthernetLite)
• Quad SPI FLash (AXI Quad SPI)
• 4 LEDs (AXI GPIO)
• 4 Push Buttons (Ch2 of 4 LEDs AXI GPIO)
• Shield Pins 0 thru 19 (AXI GPIO)
• Shield Pins 26 thru 41 (Ch2 of Shield Pins 0 thru 19 AXI GPIO)
• System Reset
• SPI connector J6 (AXI Quad SPI)
• USB Uart (AXI UartLite)

Increase the number of ports for microblaze_0_xlconcat to 5:

Then connect the interrupt outputs of the peripherals to microblaze_0_xlconcat is the following order:

• In0 - Ethernet MII (AXI EthernetLite)
• In1 - USB Uart (AXI UartLite)
• In2 - Quad SPI FLash (AXI Quad SPI)
• In3 - SPI connector J6 (AXI Quad SPI)
• In4 - Shield Pins (AXI GPIO)

Validate the Block Design (the check box icon at the top of the Block Design diagram window) to make sure there are no errors or critical warnings.

Then save the Block Design and select the option to Generate Block Design from the Flow Navigator window.

Create HDL Wrapper

Right-click on the block design file in the Sources tab, and select Create HDL Wrapper...:

Select option to allow Vivado to auto-manage it

Wait for the file structure hierarchy to update in the Sources tab. The HDL wrapper will be automatically named <block design name>_wrapper:

Generate Bitstream

There isn't a need to explicitly add a constraints file since we used all board preset connections from the Board tab in the block design as they are defined in the board preset files we selected for the Arty A7 when the project was created.

Export Hardware

Package the hardware and export for use in Vitis to develop a bare metal application. Select File > Export > Export Hardware...:

Go through the Export Wizard, be sure to select the option to include the bitstream in the exported design on the second page.

You can specify any desired output directory you prefer. I personally like to leave it set to the default location of the top level directory of the Vivado project.

At this point, all of the necessary hardware has been created and is ready for bare metal software development in Vitis.