How to design SWD interface?

For the design of the programming interface SWD, the general SWD design schemes are as follows:

• 3-wire——GND, SWDIO, SWCLK
• 4-wire——GND, SWDIO, SWCLK, VREF
• 5-wire——GND, SWDIO, SWCLK, VREF, RESET

According to the current debugging effect and the feedback of customer cases, I strongly recommend customers: Use 5-wire SWD as much as possible.

And in SWD, SWDIO pulls up a 10K resistor, and SCLK pulls down a 10K resistor.

First of all, whether it is three/four/five wire system or other methods, all wire systems need GND, SWDIO, SWCLK.

Secondly, NRST and VDD must not be connected, and SWD pull-up and pull-down problems:

#NRST, if the internal SWD module of the chip is disabled (the code that disables the SWD interface is executed in the user program), it is impossible to reprogram the chip without NRST, and why some applications do not use NRST, because the onboard hardware Power-on reset is designed.

#VREF (some people may think it is VDD) is mainly used to match the communication level on the SWDIO pin of the programmer with the IO level of the target chip. The SWDIO pin is an open-drain pin. The realization of high level comes from the pull-up resistor connected between SWDIO and VREF line inside the programmer (this resistance is the programmer’s business. Do not design it on the circuit board).

If the voltage on VREF is inconsistent with the IO voltage of the chip, it may cause a level mismatch and communication failure. That is, VREF is used to collect the chip voltage of the target board! Those who say that they can be programmed without connecting this are narrowly thinking that all The chip is powered by 3.3V, In fact, some applications are powered by 2V power supply or other voltages. So the programmer must use this pin to capture the pull-up voltage on SWDIO.

Of course, if the target chip is powered by 3.3V, and the programmer is also configured to output 3.3V, then the level itself is matched. Therefore, it is possible to communicate without connecting VREF at this time, which caused a bunch of misunderstandings. It can also be programmed without connecting VREF.

#For the SWD pull-down problem: Externally pull up SWDIO and pull down SWCLK. The pull-up and pull-down resistance is between 1 and 10K. It is mainly used for stable programming and debugging, and prevents the line from being too long or disturbing, depending on the customer's application.

Uart pull-down, depending on the actual application, generally there is a weak pull-up inside, if you really want to pull up, it is recommended within 10K, which is also a measure to improve stability.