Published June 9, 2024 © GPL3+

Ripes RISC-V Simulator

Look inside a RISC-V processor and see how it ticks

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Things used in this project

Software apps and online services

Ripes RISC-V Simulator

Story

Download and unzip Ripes simulator for your operating systems. For Linux and Windows right click on the Ripes application and open, run or execute.

Default Screen

Shows a simulator of a 5-Stage RISC-V processor. There are several other models. The popular CH32V003 chip is like this, think of it like an Arduino.

The layout or "architecture" of RISC cores is a pipeline of circuits moving data fetched from memory through writing back results. It executes parts of more than one command at one time.

Configure IO

Click on the LED icons on the left of your screen. Click on LED Matrix to bring up the display and parameter. When you get the matrix picture added then our simulator will use this data in the program.

This panel sets up whether your simulator behaves like it has a matrix of LEDs, on-off toggle switches or a joystick interface. WIDTH and HEIGHT are obvious, BASE is the starting memory address for the device.

Editor

Click on the editor icon. On first run we will see blank fields. Menu File->Load Example->Assembly->leds.s to load our program.

leds.s Example

Assembly language is not easy to read. This sketch reads the dimensions we put in for our LED matrix and runs two loops to toggle the LEDs we saw. One loop steps the program through the rows and the other loop steps through the columns.

Source code is our input program, we can edit it, save. We are writing mnemonics for the RISC-V machine language that include pseudo-instructions.

Middle panel shows hexadecimal version of the 32bit machine code. Disassembled column is re-converting from the actual machine instructions into readable assembly commands.

Bottom right corner of screen says we are working with ISA RV32IM instruction set programming language. Ripes lets us also work with 64bit RISC-V and extensions.

Select binary and we see a column with the same 32bit numbers already displayed in hexadecimal.

Play

Click the green play button at the top of the screen. The program will begin running. Middle panel shows machine level instructions being executed. Final column is the 32 registers used in this processor design.

This is a debugging tool. We can set breakpoints and single step forwards and backwards through our code. The red highlight lines are being executed by the stages of the processor.

Because of the RISC pipeline we see up to five commands executed at once. The black letters on the red highlighted lines are the stage names.

Processor

Click the processor icon. See how the machine level commands run through a 5 stage processor. These are the same commands we saw in the editor screen. The same single step menu commands work.

Click on the Play/Pause and cycle through the options. Many parameters can only be changed while the simulator is paused or stopped. The swirly icon resets the program to the start.

The red nop means no operation, the circuit pauses while the rest of the calculation catches up. We call this "stalling" and is normal.

Display options allow register values, console output, stack values. You can display binary or hex. Click, right-click and look at extra menus.

Check the IO Screen

Click on IOs and we can watch the pixels turn on and off. It's like a two dimensional blinky program.

Can we compile C/C++?

Nope, not yet. Ripes comes with example C programs but will not run them until a RISC-V compiler toolchain is installed in the computer. You'll see this screen, a lot.

Add a Compiler

Menu Edit->Settings->Compiler brings you to a panel that allows you to navigate to any toolchain installation you may have on your computer. We'll show you in another project.

Installing the complete RISC-V C/C++ compiler toolchain may take a GigaByte of storage in your computer. You can install one toolchain with MounRiver or Embeetle IDEs and use it here. When the program sees a good toolchain it shows green.

Now we can open and edit C/C++ programs and the included examples. Click the hammer icon to build and run the code. We can also load elf files from other programs.

Other Processors

RISC-V doesn't require you to use any of their models but they are designed to work with the ISA. You may have to recompile your programs as you change. Click the box icon next to the swirly while the simulator is stopped.

6-stage dual-issue processor

Notice that Bottom right corner of screen says we are working with ISA RV64IM instruction set programming language. This is a 64bit machine code and it supports extensions to add mathematical instructions.

Single Cycle RISC-V Processor

Imagine your electronic product needs programmability but not much. This computer core is so simple you could build it with relays or compressed air.

More IOs

Go back to the I/O panel and look at Switches and D-Pad. Like the LED matrix they have parameters that can be entered into your program including a memory address.

# LEDs
# This program draws an animation on an LED matrix peripheral.
#
# To run this program, make sure that you have instantiated an "LED Matrix"
# peripheral in the "I/O" tab.


li a0 LED_MATRIX_0_BASE
li a1 LED_MATRIX_0_WIDTH
li a2 LED_MATRIX_0_HEIGHT

loop:
        addi    sp, sp, -16
        sw      s0, 12(sp)
        sw      s1, 8(sp)
        mv      t6, zero
        add     t3, a2, a1
        slli    a6, a1, 2
        lui     a3, 16
        addi    a7, a3, -256
        lui     t0, 4080
init:
        mv      t4, zero
        mv      t1, zero
        mv      t2, a0
nextRow:
        mv      a4, zero
        slli    a3, t1, 8
        sub     a3, a3, t1
        divu    a3, a3, a2
        add     a3, a3, t6
        slli    a3, a3, 8
        and     t5, a3, a7
        mv      a5, t2
        mv      a3, a1
nextPixel:
        divu    s0, a4, a1
        add     s0, s0, t6
        add     s1, t4, a4
        divu    s1, s1, t3
        add     s1, s1, t6
        slli    s0, s0, 16
        and     s0, s0, t0
        or      s0, t5, s0
        andi    s1, s1, 255
        or      s0, s0, s1
        sw      s0, 0(a5)
        addi    a3, a3, -1
        addi    a5, a5, 4
        addi    a4, a4, 255
        bnez    a3, nextPixel
        addi    t6, t6, 1
        addi    t1, t1, 1
        add     t2, t2, a6
        addi    t4, t4, 255
        bne     t1, a2, nextRow
        j       init

#include "ripes_system.h"

/* LEDs
 * This program draws an animation on an LED matrix peripheral.
 *
 * To run this program, make sure that you have instantiated an "LED Matrix"
 * peripheral in the "I/O" tab.
 */

#define W LED_MATRIX_0_WIDTH
#define H LED_MATRIX_0_HEIGHT
unsigned* led_base = LED_MATRIX_0_BASE;

void main() {
    unsigned v = 0;
    while (1) {
        for (int y = 0; y < H; y++) {
            for (int x = 0; x < W; x++) {
                char r = v + (0xFF * x) / W;
                char g = v + (0xFF * y) / H;
                char b = v + (0xFF * (x + y)) / (W + H);
                unsigned idx = y * W + x;
                *(led_base + idx) = r << 16 | g << 8 | b;
            }
            v++;
        }
    }
}

Ripes RISC-V Simulator

Things used in this project

Software apps and online services

Story

Default Screen

Configure IO

Editor

leds.s Example

Play

Processor

Check the IO Screen

Can we compile C/C++?

Add a Compiler

Other Processors

6-stage dual-issue processor

Single Cycle RISC-V Processor

More IOs

Code

leds.s

leds.c

Credits

Patrick Fitzgerald

Comments

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Ripes RISC-V Simulator

Ripes RISC-V Simulator

Things used in this project

Software apps and online services

Story

Default Screen

Configure IO

Editor

leds.s Example

Play

Processor

Check the IO Screen

Can we compile C/C++?

Add a Compiler

Other Processors

6-stage dual-issue processor

Single Cycle RISC-V Processor

More IOs

Code

leds.s

leds.c

Credits

Patrick Fitzgerald

Comments

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