RISC-V Assembly Language with Ripes OnLine Simulator

RISC-V is meant to be simple. Ripes simulator online lets you run your assembly code with no installation on your computer.

Ripes.me Webpage

Go to the webpage and you see one of the model processors designed to run the RISC-V language.

Rearrange the lines to make a comfortable image. Hover your cursor and pull the lines.

Cycle through the tabs to see the different screens. We are going to focus on what we can do with Editor, Processor and IO.

IO Screen

Ripes can simulate three peripheral devices. Each with an address location in memory and other parameters. Double click the LED Matrix until your screen looks like this.

Our project needs this LED Matrix to run. leds.s is a blinky program that turns these little dots on and off. RISC-V does not have dedicated IO registers and talks to this module at a range of memory addresses beginning at 0xf0000000.

Editor Panel

Go to the Editor panel. We type our program into the Source code panel. The webpage can run a program in assembly language C/C++ requires you to add a compiler.

Load Example leds.s

Menu File->Load Example->Assembly->leds.s and Ripes will load an assembly language example. It is a sort of blinky program that will turn on LEDs in a matrix display module.

Debugging Menu

Familiar play button, forward and back arrow. The swirly icon resets our program to the start. The hammer builds C/C++ programs and we can select how fast our simulation runs.

Hover over each command and read the popup. Try things. You can always start over.

Patience

The input program panel will fill with lines of RISC-V assembly code. Slower computers will take a moment to evaluate the code and then our debugging menu will let us run it. Like a spellcheck.

After checking, the Executable Code panel in the middle of the screen will fill with our actual output program. Our input contains comments that are removed and some of our input lines become two or more lines of actual output.

Each 32bit word of executable code is 4bytes so we see addresses 0: 4: 8: and label<loop> at address c: Our input is written using Alias values and executable has Name values.

If you still do not see the middle panel fill out with disassembled code then return to the IO tab. Make sure you setup the matrix display. Menu File->Load Example with different example. Processor reset, refresh webpage and patience.

Play

Click the green play button and the simulation will start running. The moving red lines show commands passing through the processor. This program spends most of its time in the nextPixel loop incrementing to the next LED bulb.

Watch the red lines move. An instruction is fetched, executed and write back is the last step. The next instruction follows immediately behind.

Processor View

Click the Processor view and we see the same commands passing through the circuits of our simulated chip. Play/pause, step commands and processor reset work and you can select the refresh speed.

Menu View->settings to see processor signal values

IO View

We are running a kind of blinky program. We can see the lamps turn on and off. Change the ms millisecond setting to speed up the display. Look at the numbers for the display: base address 0xf0000000, width 35pixels = 0x23, height 25pixels = 0x19

Single Step

Reset the processor. You may have to pause, first. A single red line labeled IF is going into an Instruction Fetch circuit. The instruction is to load the base address of 0xf0000000 for our display. Watch the value load into register x10.

Click the single step arrow and watch the red lines. We are looking inside the RISC-V processor to see what is going on, which commands are executing and we see the registers change value.

Click the single step arrow and we see the processor load the 3 numbers we have for our display. We use program variable a0 for the base address for our display, a1 is width and a2 height. Our code uses these Aliases for the hardware circuits.

Reading RISC-V Assembly

The first instructions of our program move these numbers into processor registers x10, x11 and x12. Watch this happen in the Ripes simulator gpr general purpose register values.

From the RISC-V specification:

We write our input using the ABI application binary interface names. The executable code will use the corresponding hardware register circuits.

Processor Tab View

Select the processor tab and we will see the operations RISC-V hardware would perform executing our instructions. Repeat Play and Single Step in processor view.

Pipeline IF-ID-EX-MEM-WB

Our processor is built with circuits to perform digital calculations. By loading the next instruction as soon as the circuit is free we get a better throughput. The letters IF-ID-EX-MEM-WB show a pipeline of commands passing through the processor.

The stages are:

• IF Instruction Fetch
• ID Instruction Decode
• EX Execution
• MEM Memory
• WB Write Back

You will see red nop no operation indicators on the screen. Circuits may need an extra clock cycle to finish their work so a stage can stall to let the bits catch up. This is a normal feature.

Reset the simulation to restart. More on pipeline at Wikipedia Classic Risc Pipeline.

The Disassembled Code

The middle column is our program spellchecked to run on a RISC-V compliant processor. The first command is lui x10 0xf0000 load upper immediate value to register x10. Second command addi x11 x0 35 add immediate decimal 35 to register x11. Third command addi x12 x0 25 add immediate decimal 25 to register x12.

0:        f0000537        lui x10 0xf0000
4:        02300593        addi x11 x0 35
8:        01900613        addi x12 x0 25
0000000c <loop>:
c:        ff010113        addi x2 x2 -16
10:        00812623        sw x8 12 x2
14:        00912423        sw x9 8 x2
18:        00000f93        addi x31 x0 0
1c:        00b60e33        add x28 x12 x11
20:        00259813        slli x16 x11 2
24:        000106b7        lui x13 0x10
28:        f0068893        addi x17 x13 -256
2c:        00ff02b7        lui x5 0xff0
00000030 <init>:
30:        00000e93        addi x29 x0 0
34:        00000313        addi x6 x0 0
38:        00050393        addi x7 x10 0
0000003c <nextRow>:
3c:        00000713        addi x14 x0 0
40:        00831693        slli x13 x6 8
44:        406686b3        sub x13 x13 x6
48:        02c6d6b3        divu x13 x13 x12
4c:        01f686b3        add x13 x13 x31
50:        00869693        slli x13 x13 8
54:        0116ff33        and x30 x13 x17
58:        00038793        addi x15 x7 0
5c:        00058693        addi x13 x11 0
00000060 <nextPixel>:
60:        02b75433        divu x8 x14 x11
64:        01f40433        add x8 x8 x31
68:        00ee84b3        add x9 x29 x14
6c:        03c4d4b3        divu x9 x9 x28
70:        01f484b3        add x9 x9 x31
74:        01041413        slli x8 x8 16
78:        00547433        and x8 x8 x5
7c:        008f6433        or x8 x30 x8
80:        0ff4f493        andi x9 x9 255
84:        00946433        or x8 x8 x9
88:        0087a023        sw x8 0 x15
8c:        fff68693        addi x13 x13 -1
90:        00478793        addi x15 x15 4
94:        0ff70713        addi x14 x14 255
98:        fc0694e3        bne x13 x0 -56 <nextPixel>
9c:        001f8f93        addi x31 x31 1
a0:        00130313        addi x6 x6 1
a4:        010383b3        add x7 x7 x16
a8:        0ffe8e93        addi x29 x29 255
ac:        f8c318e3        bne x6 x12 -112 <nextRow>
b0:        f81ff06f        jal x0 -128 <init>

IO Peripherals

We can also simulate DIP switches at address 0xf0000dac and a joystick at 0xf0000db0. The Exports panels show assembly code that will be included in our sample program.

Other Processors

They all comply with RISC-V. Stop the simulator and click on the little square processor icon. Try a few. This panel shows RV32I instruction set version with M and C extensions.

MIPS is an alternative reduced instruction set architecture.

Binary View

It's easier for us to read and understand hexadecimal numbers. Binary view mode lets us see the actual ones and zeroes that go to our processor to run. It is the same value as the hexadecimal view.

C/C++ Examples

Online Ripes simulator gives an error message and sends us to Menu Edit->Settings->Compiler. I have tried adding through computer PATH variable, no success.

The Windows and Linux versions of the Ripes simulator do work with your computer operating system to let you compile and simulate C/C++ programs.

The RISCV-Xpack-Toolchain takes about a GByte of space on your computer. You can use the downloads from MounRiver and Embeetle.

Ripes does provide C/C++ example programs.