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10 dsp projects

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TinyML Made Easy: Motion Classification with Nicla Vision

Motion classification and Anomaly Detection exploration with the help of Edge Impulse and Arduino Nicla Vision.

TinyML Made Easy: Motion Classification with Nicla Vision

MJRoBot (Marcelo Rovai)
2.3K
DSP for SOMs: Getting Started with DDS & FIR Compiler IPs

This project demonstrates how to use the DDS & FIR Compiler IPs with the new AMD Kriaβ„’ KD240 Drives Starter Kit to drive analog peripherals.

DSP for SOMs: Getting Started with DDS & FIR Compiler IPs

Whitney Knitter
3.8K
Testing FIR Filters in HDL with Zmods on the Eclypse Z7

This project walks through testing FIR filters with real world signals generated by Digilent's AWG Zmod & captured with the Digitizer Zmod.

Testing FIR Filters in HDL with Zmods on the Eclypse Z7

Whitney Knitter
948
πŸšͺπŸ”” How to build an ML-powered doorbell notifier πŸ’¬

Combine real-time audio, AI/ML, DSP, and Wi-Fi connectivity technologies together to get notified when your doorbell rings while you're away

πŸšͺπŸ”” How to build an ML-powered doorbell notifier πŸ’¬

Sandeep Mistry
6.0K
DSP for FPGA: Custom AXI4-Stream FIR filter IP in Vivado

Using Vivado's built in AXI wrapper tool, this project goes over how to add an AXI4Stream interface to a custom FIR filter in Verilog.

DSP for FPGA: Custom AXI4-Stream FIR filter IP in Vivado

Whitney Knitter
7.8K
See Sound in Real-Time Using Your Raspberry Pi Pico πŸ”Š πŸ‘€

Create a real-time audio spectrogram visualizer using a Raspberry Pi Pico, digital microphone and LCD display.

See Sound in Real-Time Using Your Raspberry Pi Pico πŸ”Š πŸ‘€

Sandeep Mistry
14K
USB Webcam H264 Decode with the KV260 Vision AI Starter Kit

Learn how to use a 1080p H264 USB webcam to achieve high frame rate inference on the Xilinx Kria KV260 Vision AI starter kit.

USB Webcam H264 Decode with the KV260 Vision AI Starter Kit

Tom Simpson
4.0K
DSP for FPGA: Using Xilinx DDS with Custom FIR

See how to integrate your custom FIR with Xilinx DSP IP such as their DDS Compiler IP.

DSP for FPGA: Using Xilinx DDS with Custom FIR

Whitney Knitter
9.4K
DSP for FPGA: Rewriting FIR Logic to Meet Timing

Continuing with my simple FIR filter Verilog module, this project walks through how to rewrite HDL logic when setup timing violations occur.

DSP for FPGA: Rewriting FIR Logic to Meet Timing

Whitney Knitter
6.7K
DSP for FPGA: Simple FIR Filter in Verilog

This project walks through how to implement a simple FIR filter with pre-generated coefficients in Verilog.

DSP for FPGA: Simple FIR Filter in Verilog

Whitney Knitter
65K
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