Steve HooverAkos Hadnagy
Published © MIT

WARP-V: The Most Flexible RISC-V CPU Core Generator

WARP-V is an implementation of the RISC-V ISA that showcases the powerful modeling techniques provided by Transaction-Level Verilog.

AdvancedWork in progress5 days1,703
WARP-V: The Most Flexible RISC-V CPU Core Generator

Things used in this project

Software apps and online services

makerchip.com

Story

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Schematics

WARP-V Block Diagram

High-level block diagram with formal verification harness in red.

Code

WARP-V

See the README.

Credits

Steve Hoover
2 projects • 6 followers
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Akos Hadnagy
0 projects • 1 follower
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