This project details the installation and setup of Microchip's FPGA design tools Libero SoC Design Suite 2024.2 and SoftConsole v2022.2
A reference guide for installing the 2024.2 version AMD FPGA toolset on Ubuntu.
Lets go way back and look at the basics of FPGA design and interfacing with simple actuators
Let's learn how to get started with FPGA development. In this project we will learn about ADC on a FPGA
How to configure, and validate a FFT IP core in Vivado using various test signals
This guide provides detailed instructions for targeting the Xilinx Vitis-AI 1.2 flow for Avnet Vitis 2020.1 platforms.
This guide provides detailed instructions for targeting the Xilinx Vitis-AI 1.3 flow for Avnet Vitis 2020.2 platforms.
Remote programmer for Xilinx FPGAs via WiFi and Ethernet. Raspberry Pi + Jtag Pi board.
This guide provides detailed instructions for targeting the Xilinx Vitis-AI 1.4 flow for Avnet Vitis 2021.1 platforms.
A tutorial on creating an UART interface between the Basys 3 board and the computer terminal in VHDL running on FPGA.
This project walks through the build of an embedded Linux image for the Kria KV260 Vision AI starter kit using PetaLinux 2021.2
This project walks through how to get up and running on the ZU Board using Avnet's build scripts for Vivado & PetaLinux 2022.1
An intelligent rail inspection robot using KR260 for real-time automated fault detection, enhancing railway safety and efficiency.
Xilinx just announced Kria™, their newest product portfolio. This project takes a sneak peek at the adaptive and production ready SOM.
This project walks through how to implement a simple FIR filter with pre-generated coefficients in Verilog.
This project walks through the out-of-the-box capabilities of the Kria K260 SoM development kit.
This project walks through how to prep an Ubuntu 18.04 desktop environment and install Vivado, Vitis, & PetaLinux version 2021.
FPGA-based Binary Neural Network acceleration used for Image Classification on the Avnet Ultra96 based on the Xilinx Zynq UltraScale+ MPSoC.
The ability to process, manipulate and otherwise work with audio signals is a key feature of DSP in FPGA. Here's a look at how we do this!
This project shows the step I did to add a USB-WiFi (Realtek 8812BU) adapter to a Kria KV260 running Ubuntu 20.04.3
Creating/packaging custom PL IP, then developing PS software to write/read its memory-mapped registers.
This project walks through how to build a custom hardware design for the Kria KR260 Robotics Starter Kit in Vivado 2022.1
In this project I will show you how to create a custom AXI IP on Vitis, and the driver to manage it from Bare-Metal and Petalinux.
A quick guide for loading a static or partial accelerator at runtime in Linux.
