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708 fpga projects page 28

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WaveForms on Eclypse: Validating Basic Modulation Schemes

This project walks through how to use a Zmod Digitizer with WaveForms to make measurements that validate basic modulation schemes.

WaveForms on Eclypse: Validating Basic Modulation Schemes

Whitney Knitter
368
Image Convolution with Altera FPGAs

Altera Accelerator Image Convolution Filter Demo with Agilex 7, Arria 10, and MAX 10 FPGAs.

Image Convolution with Altera FPGAs

Andrew Wilson
364
Intel-FPGA-Quartus

Example of how to program an Altera FPGA with Intel Quartus and VHDL.

Intel-FPGA-Quartus

Victor Altamirano
357
Dual-Frequency Sin wave in Vivado Simulation by Block Memory

Dual-Frequency Sine Wave Generators in Vivado Simulation by Xilinx Block Memory Generator

Dual-Frequency Sin wave in Vivado Simulation by Block Memory

FPGAPS
339
PwFPGAs - Part 3 - SL with QP on Cyclone-IV FPGA

Prototyping with FPGAs - Part 3 - Sequential Logic with Quartus Prime on Cyclone-IV FPGA

PwFPGAs - Part 3 - SL with QP on Cyclone-IV FPGA

Yeshvanth Muniraj
334
Complete Beginner's Guide to FPGA: Adder Using Block Design

A Tutorial on how to use a FPGA and a overview on the basics of FPGA, it's uses, and how to work with one using Vivado Design Suite

Complete Beginner's Guide to FPGA: Adder Using Block Design

Risikesvar G
334
Petalinux, Vivado project for custom pcb dev-board | zynqMP

Bringing-up Xilinx ZynqMP-Ultrascale+ custom PCB dev-board with minimal Linux OS

Petalinux, Vivado project for custom pcb dev-board | zynqMP

Abdur Rehman Khalid
320
Control PWM(DC-Motor) from PYNQ and KR260

This project is part of a subproject for the AMD Pervasive AI Developer Contest. We are conducting tests with PYNQ and PWM on KR260.

Control PWM(DC-Motor) from PYNQ and KR260

misoji engineer
318
Solana proof of history acceleration

Read on to learn about interacting with the Xilinx blockchain accelerator card using Rust.

Solana proof of history acceleration

Vladimir Komendantskiy
313

Refinements and Additions! We've added a timed interrupt, improved text handling, and five new programs, including a Tic Tac Toe game.

Design and Build a 16 Bit CPU - The Next Generation

Doug Domke
311

Sequence-based redesign of Space Invaders' sound FSM using BSV (Bluespec SystemVerilog)

Sequence-based redesign of Space Invaders' sound FSM in BSV

Sakurai Atsushi
306

Traffic Lights and other PWM projects using RGB LEDs are constructed with FPGAs.

FPGA Traffic Controller

Doug Domke
285
ROS2 3D Marker from 360 Live Streaming with KR260

This project is part of a subproject for the AMD Pervasive AI Developer Contest. We process ROS2 3D Marker from 360 Live Streaming.

ROS2 3D Marker from 360 Live Streaming with KR260

misoji engineer
283
Multibit PWM IP Core Using VHDL

A multi-bit-ouptut pwm core developed in vhdl can be integrated to any softcore microprocessor system

Multibit PWM IP Core Using VHDL

Abdulraheem Nasr
283
Design and Verification of High Throughput Hamming Decoder

High Throughput decoder capable of producing an output on every input, designed using time division multiplexing of 2 Meggitt decoders.

Design and Verification of High Throughput Hamming Decoder

Shashank V M
280
Hardware-in-the-Loop Simulation with MATLAB and Zybo-Z7

HIL Simulation: MATLAB to generate signal from Picoscope, digitize it using XADC(Zybo), receive it back from PS RAM, plot, and FFT in MATLAB

Hardware-in-the-Loop Simulation with MATLAB and Zybo-Z7

Saqib Awan
273
Implementing a Configuration Memory Interface with Xilinx XC

In this project, we'll guide you through implementing a simple configuration memory interface using the XCF32P FPGA.

Implementing a Configuration Memory Interface with Xilinx XC

Loris
253
RGB to Grayscale with HW on Zynq

Two methods to convert RGB to Grayscale & Accuracy of the methods

RGB to Grayscale with HW on Zynq

Yeshvanth Muniraj
252
Autonomous robot control modelling with DNN IP generator

Have you ever try to accelerate your AI-based process? The tool we propose is able to generate a DNN IP to deploy on a dedicated hardware

Autonomous robot control modelling with DNN IP generator

Team Automation/University of Miskolc, Hungary
252
AES128 HW Accelerator on FPGA

Implementation of the AES128 Algorithm on both HW and SW

AES128 HW Accelerator on FPGA

Yeshvanth Muniraj
244
360 Live Streaming + Object Detect(DPU) with KR260

This project is part of a subproject for the AMD Pervasive AI Developer Contest. We process 360° Object Detect(DPU) with KR260.

360 Live Streaming + Object Detect(DPU) with KR260

misoji engineer
242
[RTL Design] SPI Controller for AD7303 DAC Peripheral

RTL design walkthrough for SPI Master controller to talk to AD7303 8-bit DAC peripheral.

[RTL Design] SPI Controller for AD7303 DAC Peripheral

Sameera Kumar Kambadur
235
WaveForms on Eclypse: Using a CVR to Measure Current

A walk through of how to measure the current with an oscilloscope in WaveForms using a current viewing resistor (CVR).

WaveForms on Eclypse: Using a CVR to Measure Current

Whitney Knitter
233
Dual-Frequency Sine Generator with LUT and ILA Debugging

Implement a sine wave generator on a ZCU104 board using block memory as a lookup table and clocking wizard, result demonstration with ILA

Dual-Frequency Sine Generator with LUT and ILA Debugging

FPGAPS
228
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