Using high-level synthesis, develop a hardware version of the 2D median filter algorithm (HLS). Then, apply HLS to accelerate the code utili
The Hue, Saturation, and Intensity elements control wider color range for image enhancement.
Project for Verilog practice. A watch with Arty z7 board and I2C OLED display.
The Zybo Z7-20 board, integrated with PetaLinux, supports real-time embedded vision appications using the Pcam 5C webcam.
I've wanted to learn to program FPGAs for a long time, but I struggled with where to begin. Here's how I finally got started!
This guide provides detailed steps on using Xilinx Vitis AI with Pynq and Python to create an inventory management system on the Ultra96-V2.
Want to learn about DMA and Linux Drivers? Create your own Linux Kernel Module to transfer data between PS and PL using this learning guide.
Creating a series of modules allowing you to connect for the first time a PYNQ acceleration distribution network for edge devices U96.
Prototyping with FPGAs - Part 4 - Combinational Logic vs. Sequential Logic with Vivado on Artix-7 FPGA
This project is part of a subproject for the AMD Pervasive AI Developer Contest. We conduct 360° Object Detection with YOLOX.
An open-source wheeled robot, controlled by the KR260 SoC, designed for cost-effective multispectral plant monitoring in agriculture.
This is a FPGA watch. And you can control hour/min using button. The one-second increment and the button function work together as a flow
This project has implemented UART receiver, transmitter, and flexible Polar Encoder.
This project is part of a subproject for the AMD Pervasive AI Developer Contest. We tried object detection with a regular webcam.
Design an add-on module for analog mixers that can be used to control some of the signal parameters.
Regular expression acceleration can be widely used for datacase and network applications. Tested on Xilinx Alveo U50.
ICE40UP5K FPGA module with wireless interface driven by ESP32-C3
Altering person card entry and manual tracking system to AI enabled solution using Xilinx Vitis-ai on VCK5000.
Text to speech device that can help people with low vision to read
Integration of RTL Verilog module to HLS IP'core.
How to control LEDs using using a serial protocol
Hardware POV version of "Hello, World" using Intel FPGA's MAX series CPLD or MAX10 FPGAs having both UFM and CFM.
Create a dual-core ARM application using Xilinx's Vivado and Vitis tools to control programmable logic (PL) with both A53 and R5 processors.
