Builds on the project Mini But Mightyu, the MiniZed and Vitis for Motor Control using the built in accelerometer to control the speed.
This project uses XIlinx ZCU104 to monitor fall detection using Vitis-AI and sending Alarm via SIren and IFTTT.
This write-up walks through how to fix Vitis Unified IDE 2023.2 when it does nothing but launches into a blank screen in Ubuntu.
A few IPs exposing the connections in the XDC file to the Block Design in Vivado
In this project you will learn how to implement a RISC-V processor in a SmartFusion2 SoC.
Open-source Pixblasters-Light FPGA controller drives big DIY video LED displays and shows any video by Raspberry Pi and other computers.
In this tutorial you will learn how to create Xilinx Vivado board files for your custom board.
This tutorial walks through a simple demonstration of how to deploy your testbench using Vivado's behavioral simulation.
FPGA are great for implementing Math, lets look at how we can do simple and complex Math in FPGA.
See how to integrate your custom FIR with Xilinx DSP IP such as their DDS Compiler IP.
Vivado can be run remotely on a more powerful server for improved performance while still developing on the local FPGA board
Lets go way back and look at the basics of FPGA design and interfacing with simple actuators
GigE Vision camera bridge prototype using the Zybo Z7-10 board with a Digilent Pcam 5C camera connected to it.
Learn how to configure and load bitstreams onto the C0-microSD's iCE40 FPGA across two example projects.
The article flow on how to setup interfaces as eMMC/SD in KD240 and custom carrier for K24 SoM.
This project demonstrates how to take a custom RTL module and add an AXI4-Lite interface wrapper to it for use in the Vivado block design.
Control an FPGA from the Linux OS. Dynamically reconfigure the FPGA from Linux user-space. Control custom hardware on the FPGA from Linux.
Actual PWM duty cycle on 7-segment LED display, driven by hardware (PL) and controlled by software (PS).
Creating custom applications is pretty straightforward in PetaLinux, but to debug them, Vitis comes into play.
See how to build a base hardware image for the Arty Z7 FPGA development board in Vivado 2020.2
A tutorial on controlling a Xilinx DDS Compiler IP from a bare-metal application in C running on the ARM core of the Zynq.
Let's write an efficient SRAM controller in Verilog.
How should we go about figuring out how fast the Cora Z7 is? What about using both CPU cores? What about using a full OS?
This project creates an FPGA-controlled hexapod robot which is capable of walking and navigating around its environment using sonar and IMU.