Getting Started with Infinite-ISP, the open source image signal processor on AMD Kria KV260 AI Starter kit.
We are enabling a new model of computing by providing a framework for writing web applications that utilize custom hardware acceleration.
This project provides introduction to Alveo U30 video stream transcoding and how to install and setup video SDK enviourment.
See how to control an eInk display with the UC8151D chipset from a ZynqberryZero running Adafruit's Circuit Python.
This guide provides instructions on how to monitor and display the PMBUS metrics on the Avnet Vitis 2020.1 platforms.
Let's learn everything about SRAM memories writing a controller in Verilog.
This project walks through how to create an embedded Linux image for the ARM-core in the Zynq-7000 using PetaLinux 2024.1
Adding a display to the MiniZed Motor Control live build equals an alarm clock that will be sure to start your day off on a good note.
Builds on the project Mini But Mightyu, the MiniZed and Vitis for Motor Control using the built in accelerometer to control the speed.
This write-up walks through how to fix Vitis Unified IDE 2023.2 when it does nothing but launches into a blank screen in Ubuntu.
Enabling Vitis AI 3.5 and DPU in Petalinux 2024.2 for AI/ML acceleration for Kria/MPSoC/Versal.
This project uses XIlinx ZCU104 to monitor fall detection using Vitis-AI and sending Alarm via SIren and IFTTT.
A few IPs exposing the connections in the XDC file to the Block Design in Vivado
In this project you will learn how to implement a RISC-V processor in a SmartFusion2 SoC.
Open-source Pixblasters-Light FPGA controller drives big DIY video LED displays and shows any video by Raspberry Pi and other computers.
In this tutorial you will learn how to create Xilinx Vivado board files for your custom board.
This tutorial walks through a simple demonstration of how to deploy your testbench using Vivado's behavioral simulation.
Let's learn how to get started with FPGA development. In this project we will learn about ADC on a FPGA
FPGA are great for implementing Math, lets look at how we can do simple and complex Math in FPGA.
The article flow on how to setup interfaces as eMMC/SD in KD240 and custom carrier for K24 SoM.
Vivado can be run remotely on a more powerful server for improved performance while still developing on the local FPGA board
See how to integrate your custom FIR with Xilinx DSP IP such as their DDS Compiler IP.
Lets go way back and look at the basics of FPGA design and interfacing with simple actuators
This article is on general steps and methods for creating the Vitis AI enablement project with DPU design in 2024.x tool for Kria or MPSoC.
