Let´s take a look into the I2S specification and let us try to realize the first step to play audio files with an FPGA.
Tutorial on how to use Xilinx Zynq-7000 XADC. Part 3 of 3 explains how to do write a SW application in AMD Xilinx Vitis Classic.
This tutorial is on "implementing HDMI on ZedBoard with Video Mixer and Test pattern generator".
Let's learn everything about SDR SDRAM memories by writing a controller in Verilog.
In this project we are going to implement an IIR filter in an FPGA from scratch using bilinear transform and the prewarping technique.
Using Vivado's built in AXI wrapper tool, this project goes over how to add an AXI4Stream interface to a custom FIR filter in Verilog.
Developing and Verifying a FPGA IP block requires a lot more thought than just writing the HDL. Lets take a look at how to do it!
This project walks through how to create a fixed hardware design (fixed platform) for the Zynq-7000 SoC in Vivado 2024.1.
Continuing with my simple FIR filter Verilog module, this project walks through how to rewrite HDL logic when setup timing violations occur.
SPI Interface code for Pmod ALS (8-bit ADC) in Verilog is implemented from scratch,and transmitted to 7-seg display on Basys3 FPGA board.
The aim of this project is to process LiDAR and camera data on Zybo Z7-20 to detect objects with usage of data fusion.
This project walks through a basic structure of how to transfer data between HDL in the PL to embedded C running on a processor in an FPGA.
Utilize the Zmod expansion header on the Eclypse Z7 with ADC & DAC Zmods in a simple sine wave loopback demonstration.
Swapping hardware within microseconds: Possible when using FPGAs from AMD. The technique is called Dynamic Function Exchange.
Running a simple ANN on a FPGA for MNIST with more than 200'000 fps. Using the Kria KV260 FPGA, HLS and Pynq
Demonstrating the scientific computational power of the small ZU3EG SoC by using 8 parallel floating point accelerators running at 200 MHz.
This project walks through how to integrate the required u-boot environment variables for the Zynqberry boards into a PetaLinux project.
Bring up the Ultra96 V2 in Vivado+PetaLinux 2019.2 with Wi-Fi connectivity.
Use a 1.8-inch TFT display to monitor surrounding humidity and temperature with a Zynq FPGA.
Design a stereo vision platform using a ZYNQ FPGA SOC and an FMC stereo daughtercard with DVP cameras.
FPGA based binary clock, which uses GPS for the time reference.
Run deep learning networks designed for human pose estimation on the Kria KV260 including its camera
IoT is a hot topic for Ultra96 developers. This project shows how to connect to IoT infrastructure and integrate with IFTTT.
This project demonstrates how to use the DDS & FIR Compiler IPs with the new AMD Kria™ KD240 Drives Starter Kit to drive analog peripherals.
